Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

[Pankaj Gupta]

Hi Babu,

I tried to test below patch for AMD EPYC Rome CPU and I got below error [1]:

Also, I noticed SSBD CPU flag for guest was still available even
without this patch,
I noticed that for the guest, AMD_SSBD not got set.

Guest:
0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003 edx=0x00000000

[1]
[    0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to
write 0x0000000000000000) at rIP: 0xffffffff9245c9e4
(native_write_msr+0x4/0x20)
[    0.008000]  [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50
[    0.008000]  [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80
[    0.008000]  [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0

0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP:
0xffffffff9245c772 (native_read_msr+0x2/0x40)

Thanks,
Pankaj

> > It is normally added as v2 for compatibility. Like this.
>
> o.k. Thanks!
> I will test this tomorrow.
>
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 24db7ed892..f721d0db78 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
> >          .xlevel = 0x8000001E,
> >          .model_id = "AMD EPYC-Rome Processor",
> >          .cache_info = &epyc_rome_cache_info,
> > +        .versions = (X86CPUVersionDefinition[]) {
> > +            { .version = 1 },
> > +            {
> > +                .version = 2,
> > +                .props = (PropValue[]) {
> > +                    { "ibrs", "on" },
> > +                    { "amd-ssbd", "on" },
> > +                    { "model-id",
> > +                      "AMD EPYC-Rome Processor" },
> > +                    { /* end of list */ }
> > +                }
> > +            },
> > +            { /* end of list */ }
> > +        }
> >      },
> >      {
> >          .name = "EPYC-Milan",