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[PATCH v6 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it
From: |
Bin Meng |
Subject: |
[PATCH v6 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI |
Date: |
Mon, 1 Mar 2021 21:20:06 +0800 |
From: Bin Meng <bin.meng@windriver.com>
ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
crash. This is observed when testing VxWorks 7.
We added a Xilinx CSU DMA model and the implementation is based on
https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c
and the one in Edgar's branch.
The DST part of the model is verified along with ZynqMP GQSPI model.
Changes in v6:
- int_enable and int_disable do not have its own state
- return 0 in int_enable_pre_write() and int_disable_pre_write()
- remove XLNX_CSU_DMA_INT_R_MASK in int_status_pre_write()
Changes in v5:
- int_enable and int_disable do not affect each other
- do not modify int_status int_disable_pre_write
- set MEM_DONE in xlnx_csu_dma_done if it's SRC
Changes in v4:
- Add complete CSU DMA model based on Edgar's branch
- Differences with Edgar's branch:
1. Match the registers' FIELD to UG1807.
2. Remove "byte-align" property. Per UG1807, SIZE and ADDR registers
must be word aligned.
3. Make the values of int_enable and int_disable mutually exclusive
otherwise IRQ cannot be delivered.
4. Clear int_status after int_disable is set.
5. Coding convention issues clean-up
- remove one change that is not a checkpatch warning
- Rename "csu_dma" to "qspi_dma"
- Modify XLNX_ZYNQMP_SPIPS_R_MAX
Changes in v3:
- Implement DMA as a separate CSU DMA model
- new patch: xlnx-zynqmp: Add XLNX CSU DMA module
- new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips
Changes in v2:
- Remove unconnected TYPE_STREAM_SINK link property
- Add a TYPE_MEMORY_REGION link property, to allow board codes to tell
the device what its view of the world that it is doing DMA to is
- Replace cpu_physical_memory_write() with address_space_write()
Xuzhou Cheng (5):
hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model
hw/arm: xlnx-zynqmp: Clean up coding convention issues
hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
hw/ssi: xilinx_spips: Clean up coding convention issues
hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
include/hw/arm/xlnx-zynqmp.h | 5 +-
include/hw/dma/xlnx_csu_dma.h | 52 +++
include/hw/ssi/xilinx_spips.h | 2 +-
hw/arm/xlnx-zynqmp.c | 21 +-
hw/dma/xlnx_csu_dma.c | 743 ++++++++++++++++++++++++++++++++++
hw/ssi/xilinx_spips.c | 33 +-
hw/arm/Kconfig | 1 +
hw/dma/Kconfig | 4 +
hw/dma/meson.build | 1 +
9 files changed, 838 insertions(+), 24 deletions(-)
create mode 100644 include/hw/dma/xlnx_csu_dma.h
create mode 100644 hw/dma/xlnx_csu_dma.c
--
2.25.1
- [PATCH v6 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI,
Bin Meng <=
[PATCH v6 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI, Bin Meng, 2021/03/01
[PATCH v6 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues, Bin Meng, 2021/03/01
[PATCH v6 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips, Bin Meng, 2021/03/01