Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructio

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Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructio

From:	LIU Zhiwei
Subject:	Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
Date:	Thu, 18 Feb 2021 16:39:16 +0800
User-agent:	Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0

On 2021/2/13 2:03, Richard Henderson wrote:

On 2/12/21 7:02 AM, LIU Zhiwei wrote:

+    if (a->rd && a->rs1 && a->rs2) {
+#ifdef TARGET_RISCV64
+        f64(vece, offsetof(CPURISCVState, gpr[a->rd]),
+            offsetof(CPURISCVState, gpr[a->rs1]),
+            offsetof(CPURISCVState, gpr[a->rs2]),
+            8, 8);
+#else

This is not legal tcg.

You cannot reference as memory anything which has an associated tcg_global_mem.

Thanks.

Do you mean referring a global TCGTemp as memory will cause notconsistent between TCGContext::temps and

CPUArchState field?

Zhiwei

  Which is true for all of the gprs -- see riscv_translate_init.


r~

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[PATCH 00/38] target/riscv: support packed extension v0.9.2, LIU Zhiwei, 2021/02/12
- [PATCH 02/38] target/riscv: Hoist vector functions, LIU Zhiwei, 2021/02/12
- [PATCH 03/38] target/riscv: Fixup saturate subtract function, LIU Zhiwei, 2021/02/12
  - Re: [PATCH 03/38] target/riscv: Fixup saturate subtract function, Richard Henderson, 2021/02/12
- [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei, 2021/02/12
  - Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, Richard Henderson, 2021/02/12
    - Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei <=
    - Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, Richard Henderson, 2021/02/18
  - Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, Richard Henderson, 2021/02/12
    - Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei, 2021/02/18
    - Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, Richard Henderson, 2021/02/18
- [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/02/12
- [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/02/12

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