Hey Peter,
Currently I have this test in the driver which allocates data, assign it to default value config source as the BASE address of dma, dest as the physical address which I got from dma_alloc_coherent, set the count and assign the command to
raise interrupt and read,the piece of code used is something like this(this a test performed from the probe function of the driver)
vaddr_to = dma_alloc_coherent(&(dev->dev), 4, &dma_handle_to, GFP_ATOMIC |GFP_KERNEL);
*((volatile int*)vaddr_to) = 0xff;
test->vaddr_to = vaddr_to;
dev_info(&(dev->dev), "vaddr_to = %px\n", vaddr_to);
dev_info(&(dev->dev), "dma_handle_to = %llx\n", (unsigned long long)dma_handle_to);
iowrite32(DMA_BASE, mmio + IO_DMA_SRC);
iowrite32((u32)dma_handle_to, mmio + IO_DMA_DST);
iowrite32(SIZE, mmio + IO_DMA_CNT);
iowrite32(DMA_CMD | DMA_FROM_DEV | DMA_IRQ, mmio + IO_DMA_CMD);
Where and when should the pci_set_master hould be called?
Thanks,
Shaked Matzner
From: Peter Maydell <peter.maydell@linaro.org>
Sent: Thursday, October 29, 2020 5:46 PM
To: Shaked Matzner <shaked.m@neuroblade.ai>
Cc: qemu-devel@nongnu.org
Subject: Re: simple example of pci driver with dma
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On Thu, 29 Oct 2020 at 14:59, Shaked Matzner wrote:
> however the value I get is still 255(0xff) and not 18(0x12) probably I've missed something but when the interrupt is called the transfer to the RAM address should be completed, however it seems like the dma_write_buffer function from the device does not perform
any transfer. What Am I missing?
The usual mistake is forgetting in the guest code to program the
PCI device to enable bus mastering by setting the Bus Master bit
in the Command register in the PCI config space registers for
the device. Unless you do that then all DMA attempts will fail
(same as on real h/w). In the Linux kernel the function for this
is pci_set_master(), I think.
thanks
-- PMM
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