[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 07/18] target/riscv: Add V extension state description
From: |
Alistair Francis |
Subject: |
[PULL 07/18] target/riscv: Add V extension state description |
Date: |
Thu, 29 Oct 2020 07:13:47 -0700 |
From: Yifei Jiang <jiangyifei@huawei.com>
In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ae60050898..44d4015bd6 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH);
}
+static bool vector_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVV);
+}
+
+static const VMStateDescription vmstate_vector = {
+ .name = "cpu/vector",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = vector_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu = {
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
&vmstate_hyper,
+ &vmstate_vector,
NULL
}
};
--
2.28.0
- [PULL 00/18] riscv-to-apply queue, Alistair Francis, 2020/10/29
- [PULL 02/18] hw/riscv: virt: Allow passing custom DTB, Alistair Francis, 2020/10/29
- [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit, Alistair Francis, 2020/10/29
- [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB, Alistair Francis, 2020/10/29
- [PULL 05/18] target/riscv: Add PMP state description, Alistair Francis, 2020/10/29
- [PULL 06/18] target/riscv: Add H extension state description, Alistair Francis, 2020/10/29
- [PULL 04/18] target/riscv: Add basic vmstate description of CPU, Alistair Francis, 2020/10/29
- [PULL 07/18] target/riscv: Add V extension state description,
Alistair Francis <=
- [PULL 08/18] target/riscv: Add sifive_plic vmstate, Alistair Francis, 2020/10/29
- [PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Alistair Francis, 2020/10/29
- [PULL 10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/10/29
- [PULL 12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/10/29
- [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Alistair Francis, 2020/10/29
- [PULL 13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Alistair Francis, 2020/10/29
- [PULL 15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/10/29
- [PULL 14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/10/29
- [PULL 16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Alistair Francis, 2020/10/29
- [PULL 17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map, Alistair Francis, 2020/10/29