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[PATCH v2 1/5] target/riscv: Add a virtualised MMU Mode
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 1/5] target/riscv: Add a virtualised MMU Mode |
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Date: |
Wed, 28 Oct 2020 07:42:20 -0700 |
Add a new MMU mode that includes the current virt mode.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-param.h | 10 +++++++++-
target/riscv/cpu.h | 4 +++-
target/riscv/cpu_helper.c | 6 +++++-
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 664fc1d371..0db6e23140 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -18,6 +18,14 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
-#define NB_MMU_MODES 4
+/*
+ * The current MMU Modes are:
+ * - U mode 0b000
+ * - S mode 0b001
+ * - M mode 0b011
+ * - HU mode 0b100
+ * - HS mode 0b101
+ */
+#define NB_MMU_MODES 6
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87b68affa8..5d8e54c426 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
+#define TB_FLAGS_MMU_MASK 7
+#define TB_FLAGS_PRIV_MMU_MASK 3
+#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
typedef CPURISCVState CPUArchState;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3eb3a034db..453e4c6d8a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -30,6 +30,10 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#ifdef CONFIG_USER_ONLY
return 0;
#else
+ if (riscv_cpu_virt_enabled(env)) {
+ return env->priv | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+ }
+
return env->priv;
#endif
}
@@ -323,7 +327,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
* (riscv_cpu_do_interrupt) is correct */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- int mode = mmu_idx;
+ int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
/*
--
2.28.0
- [PATCH v2 0/5] Fix the Hypervisor access functions, Alistair Francis, 2020/10/28
- [PATCH v2 1/5] target/riscv: Add a virtualised MMU Mode,
Alistair Francis <=
- [PATCH v2 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses, Alistair Francis, 2020/10/28
- [PATCH v2 3/5] target/riscv: Remove the HS_TWO_STAGE flag, Alistair Francis, 2020/10/28
- [PATCH v2 4/5] target/riscv: Remove the hyp load and store functions, Alistair Francis, 2020/10/28
- [PATCH v2 5/5] target/riscv: Split the Hypervisor execute load helpers, Alistair Francis, 2020/10/28