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Re: [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look a
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps |
Date: |
Wed, 28 Oct 2020 07:07:18 -0700 |
On Tue, Oct 27, 2020 at 10:31 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> It is not easy to find out the memory map for a specific component
> in the PolarFire SoC as the information is scattered in different
> documents. Add some comments so that people can know where to get
> such information from the Microchip website.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - new patch: Document where to look at the PolarFire SoC memory maps
>
> hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179..6aac849 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -66,6 +66,24 @@
> /* GEM version */
> #define GEM_REVISION 0x0107010c
>
> +/*
> + * The complete description of the whole PolarFire SoC memory map is
> scattered
> + * in different documents. There are several places to look at for memory
> maps:
> + *
> + * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
> + * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
> + * https://www.microsemi.com/document-portal/doc_download/
> + *
> 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
> + * describes the whole picture of the PolarFire SoC memory map.
> + *
> + * 2 A zip file for PolarFire soC memory map, which can be downloaded from
> + * https://www.microsemi.com/document-portal/doc_download/
> + * 1244581-polarfire-soc-register-map, contains the following 2 major
> parts:
> + * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
> + * describes the complete integrated peripherals memory map
> + * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
> + * describes the complete IOSCB modules memory maps
> + */
> static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> --
> 2.7.4
>
>
- [PATCH v2 00/10] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box, Bin Meng, 2020/10/28
- [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Bin Meng, 2020/10/28
- Re: [PATCH v2 01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps,
Alistair Francis <=
- [PATCH v2 02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Bin Meng, 2020/10/28
- [PATCH v2 03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Bin Meng, 2020/10/28
- [PATCH v2 05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Bin Meng, 2020/10/28
- [PATCH v2 04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Bin Meng, 2020/10/28
- [PATCH v2 06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Bin Meng, 2020/10/28
- [PATCH v2 07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Bin Meng, 2020/10/28
- [PATCH v2 08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Bin Meng, 2020/10/28
- [PATCH v2 09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map, Bin Meng, 2020/10/28