[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v1 03/16] riscv: virt: Remove target macro conditionals
From: |
Alistair Francis |
Subject: |
[PATCH v1 03/16] riscv: virt: Remove target macro conditionals |
Date: |
Fri, 23 Oct 2020 08:33:21 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 6 ------
hw/riscv/virt.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b4ed9a32eb..84b7a3848f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -89,10 +89,4 @@ enum {
#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
-#if defined(TARGET_RISCV32)
-#define VIRT_CPU TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-#define VIRT_CPU TYPE_RISCV_CPU_BASE64
-#endif
-
#endif
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6bfd10dfc7..5f1fcebdc6 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -693,7 +693,7 @@ static void virt_machine_class_init(ObjectClass *oc, void
*data)
mc->desc = "RISC-V VirtIO board";
mc->init = virt_machine_init;
mc->max_cpus = VIRT_CPUS_MAX;
- mc->default_cpu_type = VIRT_CPU;
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
mc->pci_allow_0_address = true;
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
--
2.28.0
- [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess, Alistair Francis, 2020/10/23
- [PATCH v1 01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/10/23
- [PATCH v1 02/16] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/10/23
- [PATCH v1 03/16] riscv: virt: Remove target macro conditionals,
Alistair Francis <=
- [PATCH v1 04/16] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 05/16] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 06/16] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/10/23
- [PATCH v1 07/16] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/10/23