Re: [PATCH v3 34/81] target/arm: Implement SVE2 WHILERW, WHILEWR

[Richard Henderson]

On 10/12/20 7:33 PM, LIU Zhiwei wrote:
>> +    if (a->rw) {
>> +        /* WHILERW */
>> +        /* diff = abs(op1 - op0), noting that op0/1 are unsigned. */
>> +        t1 = tcg_temp_new_i64();
>> +        tcg_gen_sub_i64(diff, op0, op1);
>> +        tcg_gen_sub_i64(t1, op1, op0);
>> +        tcg_gen_movcond_i64(TCG_COND_LTU, diff, op0, op1, diff, t1);
> It should be:
> 
> tcg_gen_movcond_i64(TCG_COND_GTU, diff, op0, op1, diff, t1);

Yep.

> 
>> +        tcg_temp_free_i64(t1);
>> +        /* If op1 == op0, diff == 0, and the condition is always true. */
>> +        tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff);
>> +    } else {
>> +        /* WHILEWR */
>> +        tcg_gen_sub_i64(diff, op1, op0);
>> +        /* If op0 >= op1, diff <= 0, the condition is always true. */
>> +        tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff);
>> +    }
>> +
>> +    /* Bound to the maximum.  */
>> +    tcg_gen_umin_i64(diff, diff, tmax);
>> +    tcg_temp_free_i64(tmax);
>> +
>> +    /* Since we're bounded, pass as a 32-bit type.  */
>> +    t2 = tcg_temp_new_i32();
>> +    tcg_gen_extrl_i64_i32(t2, diff);
> We should align count down to (1 << esz),
> 
> tcg_gen_andi_i32(t2，~MAKE_64BIT_MASK(0, esz));

Yep, this corresponds to the "DIV (esize DIV 8)" portion of the psuedo code.
But it needs to go earlier, before we compare diff against 0 in the two movcond
above.

Will fix.  Thanks,


r~