Re: [PATCH v2 02/10] target/arm: Implement v8.1M NOCP handling

[Richard Henderson]

On 10/19/20 8:12 AM, Peter Maydell wrote:
> From v8.1M, disabled-coprocessor handling changes slightly:
>  * coprocessors 8, 9, 14 and 15 are also governed by the
>    cp10 enable bit, like cp11
>  * an extra range of instruction patterns is considered
>    to be inside the coprocessor space
> 
> We previously marked these up with TODO comments; implement the
> correct behaviour.
> 
> Unfortunately there is no ID register field which indicates this
> behaviour.  We could in theory test an unrelated ID register which
> indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch
>> = 3 (low-overhead-loops), but it seems better to simply define a new
> ARM_FEATURE_V8_1M feature flag and use it for this and other
> new-in-v8.1M behaviour that isn't identifiable from the ID registers.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/cpu.h               |  1 +
>  target/arm/m-nocp.decode       | 10 ++++++----
>  target/arm/translate-vfp.c.inc | 17 +++++++++++++++--
>  3 files changed, 22 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~