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Re: [PATCH 4/5] target/riscv: Add V extention state description


From: Richard Henderson
Subject: Re: [PATCH 4/5] target/riscv: Add V extention state description
Date: Thu, 1 Oct 2020 12:30:21 -0500
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

On 9/28/20 9:03 PM, Yifei Jiang wrote:
> In the case of supporting V extention, add V extention description
> to vmstate_riscv_cpu.
> 
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  target/riscv/machine.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Though of course this is racing with the v1.0 patch set, which changes the set
of vector csrs.


r~



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