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[PATCH v6 09/10] i386: Simplify CPUID_8000_001E for AMD
From: |
Babu Moger |
Subject: |
[PATCH v6 09/10] i386: Simplify CPUID_8000_001E for AMD |
Date: |
Mon, 31 Aug 2020 13:43:01 -0500 |
User-agent: |
StGit/unknown-version |
Remove all the hardcoded values and replace with generalized
fields.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ba4667b33c..d434c8545a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -395,9 +395,10 @@ static int cores_in_core_complex(int nr_cores)
}
/* Encode cache info for CPUID[8000001D] */
-static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
- uint32_t *eax, uint32_t *ebx,
- uint32_t *ecx, uint32_t *edx)
+static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
uint32_t l3_cores;
assert(cache->size == cache->line_size * cache->associativity *
@@ -408,10 +409,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache, CPUState *cs,
/* L3 is shared among multiple cores */
if (cache->level == 3) {
- l3_cores = cores_in_core_complex(cs->nr_cores);
- *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
+ l3_cores = DIV_ROUND_UP((topo_info->cores_per_die *
+ topo_info->threads_per_core),
+ topo_info->dies_per_pkg);
+ *eax |= (l3_cores - 1) << 14;
} else {
- *eax |= ((cs->nr_threads - 1) << 14);
+ *eax |= ((topo_info->threads_per_core - 1) << 14);
}
assert(cache->line_size > 0);
@@ -5994,20 +5997,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
}
switch (count) {
case 0: /* L1 dcache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
- encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
- eax, ebx, ecx, edx);
+ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
+ &topo_info, eax, ebx, ecx, edx);
break;
default: /* end of info */
*eax = *ebx = *ecx = *edx = 0;
- [PATCH v6 00/10] Remove EPYC mode apicid decode and use generic decode, Babu Moger, 2020/08/31
- [PATCH v6 00/10] Remove EPYC mode apicid decode and use generic decode, Babu Moger, 2020/08/31
- [PATCH v6 01/10] Revert "i386: Fix pkg_id offset for EPYC cpu models", Babu Moger, 2020/08/31
- [PATCH v6 02/10] Revert "target/i386: Enable new apic id encoding for EPYC based cpus models", Babu Moger, 2020/08/31
- [PATCH v6 03/10] Revert "hw/i386: Move arch_id decode inside x86_cpus_init", Babu Moger, 2020/08/31
- [PATCH v6 04/10] Revert "i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition", Babu Moger, 2020/08/31
- [PATCH v6 05/10] Revert "hw/i386: Introduce apicid functions inside X86MachineState", Babu Moger, 2020/08/31
- [PATCH v6 06/10] Revert "target/i386: Cleanup and use the EPYC mode topology functions", Babu Moger, 2020/08/31
- [PATCH v6 07/10] Revert "hw/386: Add EPYC mode topology decoding functions", Babu Moger, 2020/08/31
- [PATCH v6 08/10] Revert "hw/i386: Update structures to save the number of nodes per package", Babu Moger, 2020/08/31
- [PATCH v6 09/10] i386: Simplify CPUID_8000_001E for AMD,
Babu Moger <=
- [PATCH v6 10/10] i386: Simplify CPUID_8000_001E for AMD, Babu Moger, 2020/08/31