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[PATCH v2 14/45] target/arm: Use macros instead of open-coding fp16 conv
From: |
Peter Maydell |
Subject: |
[PATCH v2 14/45] target/arm: Use macros instead of open-coding fp16 conversion helpers |
Date: |
Fri, 28 Aug 2020 19:33:23 +0100 |
Now the VFP_CONV_FIX macros can handle fp16's distinction between the
width of the operation and the width of the type used to pass operands,
use the macros rather than the open-coded functions.
This creates an extra six helper functions, all of which we are going
to need for the AArch32 VFP fp16 instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 6 +++
target/arm/vfp_helper.c | 86 +++--------------------------------------
2 files changed, 12 insertions(+), 80 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 18afad634c9..03193728476 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -164,6 +164,10 @@ DEF_HELPER_2(vfp_tosizh, s32, f16, ptr)
DEF_HELPER_2(vfp_tosizs, s32, f32, ptr)
DEF_HELPER_2(vfp_tosizd, s32, f64, ptr)
+DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr)
+DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr)
DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr)
DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr)
DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr)
@@ -202,6 +206,8 @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
+DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr)
+DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr)
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 7650890d440..ab3f0b170a7 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -434,92 +434,18 @@ VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
+VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16)
+VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32)
+VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
+VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
+VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
+VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
#undef VFP_CONV_FIX
#undef VFP_CONV_FIX_FLOAT
#undef VFP_CONV_FLOAT_FIX_ROUND
#undef VFP_CONV_FIX_A64
-uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
-{
- return int32_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
-{
- return uint32_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
-{
- return int64_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
-{
- return uint64_to_float16_scalbn(x, -shift, fpst);
-}
-
-uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
-uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
-{
- if (unlikely(float16_is_any_nan(x))) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst),
- shift, fpst);
-}
-
/* Set the current fp rounding mode and return the old one.
* The argument is a softfloat float_round_ value.
*/
--
2.20.1
- [PATCH v2 00/45] target/arm: Implement fp16 for AArch32 VFP and Neon, Peter Maydell, 2020/08/28
- [PATCH v2 01/45] target/arm: Remove local definitions of float constants, Peter Maydell, 2020/08/28
- [PATCH v2 02/45] target/arm: Use correct ID register check for aa32_fp16_arith, Peter Maydell, 2020/08/28
- [PATCH v2 03/45] target/arm: Implement VFP fp16 for VFP_BINOP operations, Peter Maydell, 2020/08/28
- [PATCH v2 07/45] target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp(), Peter Maydell, 2020/08/28
- [PATCH v2 06/45] target/arm: Implement VFP fp16 for fused-multiply-add, Peter Maydell, 2020/08/28
- [PATCH v2 09/45] target/arm: Implement VFP fp16 for VMOV immediate, Peter Maydell, 2020/08/28
- [PATCH v2 04/45] target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL, Peter Maydell, 2020/08/28
- [PATCH v2 05/45] target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS, Peter Maydell, 2020/08/28
- [PATCH v2 08/45] target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT, Peter Maydell, 2020/08/28
- [PATCH v2 14/45] target/arm: Use macros instead of open-coding fp16 conversion helpers,
Peter Maydell <=
- [PATCH v2 10/45] target/arm: Implement VFP fp16 VCMP, Peter Maydell, 2020/08/28
- [PATCH v2 11/45] target/arm: Implement VFP fp16 VLDR and VSTR, Peter Maydell, 2020/08/28
- [PATCH v2 15/45] target/arm: Implement VFP fp16 VCVT between float and fixed-point, Peter Maydell, 2020/08/28
- [PATCH v2 12/45] target/arm: Implement VFP fp16 VCVT between float and integer, Peter Maydell, 2020/08/28
- [PATCH v2 13/45] target/arm: Make VFP_CONV_FIX macros take separate float type and float size, Peter Maydell, 2020/08/28
- [PATCH v2 17/45] target/arm: Implement VFP fp16 VSEL, Peter Maydell, 2020/08/28
- [PATCH v2 20/45] target/arm: Implement new VFP fp16 insn VMOVX, Peter Maydell, 2020/08/28
- [PATCH v2 16/45] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode, Peter Maydell, 2020/08/28
- [PATCH v2 19/45] target/arm: Implement new VFP fp16 insn VINS, Peter Maydell, 2020/08/28
- [PATCH v2 18/45] target/arm: Implement VFP fp16 VRINT*, Peter Maydell, 2020/08/28