Re: [PATCH 64/77] target/microblaze: Convert mbar to decodetree

[Richard Henderson]

On 8/27/20 3:08 AM, Edgar E. Iglesias wrote:
>> Ok.  I assume this follows a write to something like an interrupt controller
>> register?
> 
> yes, kind of. It's a memory store to a device that raises an interrupt as a
> result of that store. The interrupt propagates to the CPU and on real HW if
> the pipeline depth of the core is small, it gets taken within a couple of
> cycles after the barrier completes. In QEMU, that delay can become very long
> if we don't break the TB.

Ok, yeah, same idea.  The data store alters the set of interrupts pending.

> Architecturally, it would be wrong to make such assumptions about the pipeline
> but there's code out there already..

Yes indeed.


r~