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[PATCH RFC v3 11/14] target/riscv: Support riscv cpu vmstate
From: |
Yifei Jiang |
Subject: |
[PATCH RFC v3 11/14] target/riscv: Support riscv cpu vmstate |
Date: |
Thu, 27 Aug 2020 17:21:34 +0800 |
Describe gpr, fpr and csr in vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/cpu.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d8c32a8f84..b698f4adbb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -26,7 +26,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/qdev-properties.h"
-#include "migration/vmstate.h"
+#include "migration/cpu.h"
#include "fpu/softfloat-helpers.h"
#include "kvm_riscv.h"
@@ -499,7 +499,23 @@ static void riscv_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .unmigratable = 1,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+ VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+ VMSTATE_UINTTL(env.pc, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.mie, RISCVCPU),
+ VMSTATE_UINTTL(env.stvec, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc, RISCVCPU),
+ VMSTATE_UINTTL(env.scause, RISCVCPU),
+ VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.mip, RISCVCPU),
+ VMSTATE_UINTTL(env.satp, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
};
#endif
--
2.19.1
- [PATCH RFC v3 00/14] Add riscv kvm accel support, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 03/14] target/riscv: Implement function kvm_arch_init_vcpu, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 01/14] linux-header: Update linux/kvm.h, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 05/14] arget/riscv: Implement kvm_arch_put_registers, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 06/14] target/riscv: Support start kernel directly by KVM, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 11/14] target/riscv: Support riscv cpu vmstate,
Yifei Jiang <=
- [PATCH RFC v3 14/14] target/riscv: Support virtual time context synchronization, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 10/14] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 13/14] target/riscv: Implement virtual time adjusting with vm state changing, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 08/14] target/riscv: Handler KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 02/14] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 09/14] target/riscv: Add host cpu type, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 07/14] hw/riscv: PLIC update external interrupt by KVM when kvm enabled, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 04/14] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 2020/08/27
- [PATCH RFC v3 12/14] target/riscv: Add kvm_riscv_get/put_regs_timer, Yifei Jiang, 2020/08/27