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[PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instruct
From: |
Alistair Francis |
Subject: |
[PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions |
Date: |
Tue, 25 Aug 2020 11:48:26 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com
Message-Id:
<024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 60 ++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e5e0d80c32..5efb3b16e0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
+ if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
+ use_background = true;
+ }
+
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
-
- if (riscv_has_ext(env, RVH) &&
- MSTATUS_MPV_ISSET(env)) {
- use_background = true;
- }
- }
- }
-
- if (mode == PRV_S && access_type != MMU_INST_FETCH &&
- riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
- if (get_field(env->hstatus, HSTATUS_SPRV)) {
- mode = get_field(env->mstatus, SSTATUS_SPP);
- use_background = true;
}
}
@@ -608,7 +599,8 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
}
break;
case MMU_DATA_LOAD:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+ !first_stage) {
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -616,7 +608,8 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
}
break;
case MMU_DATA_STORE:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+ !first_stage) {
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -706,8 +699,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
hwaddr pa = 0;
int prot, prot2;
bool pmp_violation = false;
- bool m_mode_two_stage = false;
- bool hs_mode_two_stage = false;
bool first_stage_error = true;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
@@ -718,30 +709,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- /*
- * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
- * set and we want to access a virtulisation address.
- */
- if (riscv_has_ext(env, RVH)) {
- m_mode_two_stage = env->priv == PRV_M &&
- access_type != MMU_INST_FETCH &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- MSTATUS_MPV_ISSET(env);
-
- hs_mode_two_stage = env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env) &&
- access_type != MMU_INST_FETCH &&
- get_field(env->hstatus, HSTATUS_SPRV) &&
- get_field(env->hstatus, HSTATUS_SPV);
- }
-
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
- if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+ }
+
+ if (riscv_cpu_virt_enabled(env) ||
+ (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address, access_type,
mmu_idx, true, true);
@@ -793,6 +775,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
__func__, address, ret, pa, prot);
}
+ /* We did the two stage lookup based on MPRV, unset the lookup */
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, false);
+ }
+
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--
2.28.0
- [PULL 00/18] riscv-to-apply queue, Alistair Francis, 2020/08/25
- [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT, Alistair Francis, 2020/08/25
- [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC, Alistair Francis, 2020/08/25
- [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines, Alistair Francis, 2020/08/25
- [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/25
- [PULL 05/18] hw/riscv: virt: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/25
- [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions,
Alistair Francis <=
- [PULL 09/18] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/25
- [PULL 11/18] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/25
- [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/25
- [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/25
- [PULL 14/18] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/25
- [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/25
- [PULL 15/18] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/25
- [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/25
- [PULL 18/18] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/25
- Re: [PULL 00/18] riscv-to-apply queue, Peter Maydell, 2020/08/25