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[PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
From: |
Richard Henderson |
Subject: |
[PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp |
Date: |
Fri, 14 Aug 2020 18:31:32 -0700 |
The gvec operation was added after the initial implementation
of the SEL instruction and was missed in the conversion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 31 ++++++++-----------------------
1 file changed, 8 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 13a0194d59..aa7ed070e3 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1188,34 +1188,19 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s
*a)
return do_pppp_flags(s, a, &op);
}
-static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
-{
- tcg_gen_and_i64(pn, pn, pg);
- tcg_gen_andc_i64(pm, pm, pg);
- tcg_gen_or_i64(pd, pn, pm);
-}
-
-static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn,
- TCGv_vec pm, TCGv_vec pg)
-{
- tcg_gen_and_vec(vece, pn, pn, pg);
- tcg_gen_andc_vec(vece, pm, pm, pg);
- tcg_gen_or_vec(vece, pd, pn, pm);
-}
-
static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
{
- static const GVecGen4 op = {
- .fni8 = gen_sel_pg_i64,
- .fniv = gen_sel_pg_vec,
- .fno = gen_helper_sve_sel_pppp,
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
- };
-
if (a->s) {
return false;
}
- return do_pppp_flags(s, a, &op);
+ if (sve_access_check(s)) {
+ unsigned psz = pred_gvec_reg_size(s);
+ tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd),
+ pred_full_reg_offset(s, a->pg),
+ pred_full_reg_offset(s, a->rn),
+ pred_full_reg_offset(s, a->rm), psz, psz);
+ }
+ return true;
}
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
--
2.25.1
- [PATCH 16/20] target/arm: Fix sve_zip_p vs odd vector lengths, (continued)
- [PATCH 16/20] target/arm: Fix sve_zip_p vs odd vector lengths, Richard Henderson, 2020/08/15
- [PATCH 01/20] qemu/int128: Add int128_lshift, Richard Henderson, 2020/08/15
- [PATCH 20/20] target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 13/20] target/arm: Tidy SVE tszimm shift formats, Richard Henderson, 2020/08/15
- [PATCH 09/20] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/08/15
- [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp,
Richard Henderson <=
- [PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/08/15
- [PATCH 17/20] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2020/08/15
- [PATCH 19/20] target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 11/20] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/08/15
- [PATCH 04/20] target/arm: Rearrange {sve,fp}_check_access assert, Richard Henderson, 2020/08/15