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[RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing ve
From: |
frank . chang |
Subject: |
[RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers |
Date: |
Thu, 6 Aug 2020 18:46:07 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11ce6d4576a..50a178a60d0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -60,6 +60,11 @@ static int fs(CPURISCVState *env, int csrno)
static int vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+#endif
return 0;
}
return -1;
--
2.17.1
- [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field, (continued)
- [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/08/06
- [RFC v3 04/71] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/08/06
- [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2020/08/06
- [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/06
- [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/08/06
- [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/06
- [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/06
- [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers,
frank . chang <=
- [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/06
- [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/06
- [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/06
- [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/08/06
- [RFC v3 16/71] target/riscv: add fp16 nan-box check generator function, frank . chang, 2020/08/06