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Re: [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register inst
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions |
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Date: |
Wed, 29 Jul 2020 13:30:09 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> +static void
> +vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t
> desc,
> + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
> + MMUAccessType access_type)
> +{
> + uint32_t i, k;
> + uint32_t nf = vext_nf(desc);
> + uint32_t vlmax = vext_maxsz(desc) / esz;
> + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +
> + /* probe every access */
> + probe_pages(env, base, vlenb * nf * esz, ra, access_type);
> +
> + /* load bytes from guest memory */
> + for (i = 0; i < vlenb; i++) {
> + k = 0;
> + while (k < nf) {
> + target_ulong addr = base + (i * nf + k) * esz;
> + ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + k++;
> + }
> + }
> +}
First, nf != 0 is reserved, so you shouldn't attempt to support it here.
Second, even then the note in the spec suggests that these two loops should be
interchanged -- but I'll also grant that the language could use improvement.
Indeed, the whole vector load/store section seems to need improvement. For
instance, no where does it say how EEW < SEW load operations are extended.
>From reading Spike source code I can infer that it's sign-extended. But that's
something a spec should explicitly say.
r~
- Re: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper, (continued)
- [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans, frank . chang, 2020/07/22
- [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/22
- [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/22
- [RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/22
- [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/22
- [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/22
- [RFC v2 26/76] target/riscv: rvv-0.9: amo operations, frank . chang, 2020/07/22
- [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/22
- Re: [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions,
Richard Henderson <=
- [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/22
- [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation, frank . chang, 2020/07/22
- [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/22
- [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/22
- [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/22