[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs

[Sanjay Basu]

h-sieger, 
I did some testing with geekbench 5:

baseline multicore score = 12733
https://browser.geekbench.com/v5/cpu/3069626

score with <cache="passthrough"> option = 12775
https://browser.geekbench.com/v5/cpu/3069415

best score with your xml above = 16960
https://browser.geekbench.com/v5/cpu/3066003

I'm running a 3960x and it is 3 cores per CCX so your xml above works well. I'm 
just now learning about all this so I'm still trying to figure out how to 
modify your xml to assign more cores. Anyway, I'm getting better performance 
out of my Windows 10 VM now assigning 24 vcpu as opposed to the 32 that I was 
assigning before!
By the way, I tried to email you directly because I'm not sure this is 
appropriate discussion for this bug report but I could not create an account on 
your website (captcha was malfunctioning). Hope you you can fix that soon.

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https://bugs.launchpad.net/bugs/1856335

Title:
  Cache Layout wrong on many Zen Arch CPUs

Status in QEMU:
  New

Bug description:
  AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
  to always map Cache ass if it was an 4-Core per CCX CPU, which is
  incorrect, and costs upwards 30% performance (more realistically 10%)
  in L3 Cache Layout aware applications.

  Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):

    <cpu mode='custom' match='exact' check='full'>
      <model fallback='forbid'>EPYC-IBPB</model>
      <vendor>AMD</vendor>
      <topology sockets='1' cores='8' threads='1'/>

  In windows, coreinfo reports correctly:

  ****----  Unified Cache 1, Level 3,    8 MB, Assoc  16, LineSize  64
  ----****  Unified Cache 6, Level 3,    8 MB, Assoc  16, LineSize  64

  On a 3-CCX CPU (3960X /w 6 cores and no SMT):

   <cpu mode='custom' match='exact' check='full'>
      <model fallback='forbid'>EPYC-IBPB</model>
      <vendor>AMD</vendor>
      <topology sockets='1' cores='6' threads='1'/>

  in windows, coreinfo reports incorrectly:

  ****--  Unified Cache  1, Level 3,    8 MB, Assoc  16, LineSize  64
  ----**  Unified Cache  6, Level 3,    8 MB, Assoc  16, LineSize  64

  Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.

  With newer Qemu there is a fix (that does behave correctly) in using the dies 
parameter:
   <qemu:arg value='cores=3,threads=1,dies=2,sockets=1'/>

  The problem is that the dies are exposed differently than how AMD does
  it natively, they are exposed to Windows as sockets, which means, that
  if you are nto a business user, you can't ever have a machine with
  more than two CCX (6 cores) as consumer versions of Windows only
  supports two sockets. (Should this be reported as a separate bug?)

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