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[PULL 3/5] target/riscv: fix vector index load/store constraints
From: |
Alistair Francis |
Subject: |
[PULL 3/5] target/riscv: fix vector index load/store constraints |
Date: |
Wed, 22 Jul 2020 09:48:36 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.
And this constraint has been added to the v0.8 spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 7b4752b911..887c6b8883 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a,
uint8_t seq)
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
+/*
+ * For vector indexed segment loads, the destination vector register
+ * groups cannot overlap the source vector register group (specified by
+ * `vs2`), else an illegal instruction exception is raised.
+ */
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
+ vext_check_nf(s, a->nf) &&
+ ((a->nf == 1) ||
+ vext_check_overlap_group(a->rd, a->nf << s->lmul,
+ a->rs2, 1 << s->lmul)));
}
GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
--
2.27.0
- [PULL 0/5] riscv-to-apply queue, Alistair Francis, 2020/07/22
- [PULL 1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH, Alistair Francis, 2020/07/22
- [PULL 2/5] target/riscv: Quiet Coverity complains about vamo*, Alistair Francis, 2020/07/22
- [PULL 4/5] hw/riscv: sifive_e: Correct debug block size, Alistair Francis, 2020/07/22
- [PULL 3/5] target/riscv: fix vector index load/store constraints,
Alistair Francis <=
- [PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table, Alistair Francis, 2020/07/22
- Re: [PULL 0/5] riscv-to-apply queue, Peter Maydell, 2020/07/24