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[RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions
From: |
frank . chang |
Subject: |
[RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions |
Date: |
Wed, 22 Jul 2020 17:16:05 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvv.inc.c | 27 +++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4be1b88e2d..0e1d6b3ead 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -595,6 +595,10 @@ vrgather_vv 001100 . ..... ..... 000 ..... 1010111
@r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
+vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
+vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
+vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
+vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 56cd7444f2..85f22a1495 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3527,3 +3527,30 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
}
return false;
}
+
+/*
+ * Whole Vector Register Move Instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 17.6)
+ */
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ if (require_rvv(s) && \
+ ((a->rd & ((LEN) - 1)) == 0) && \
+ ((a->rs2 & ((LEN) - 1)) == 0)) { \
+ for (int i = 0; i < LEN; ++i) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(8, vreg_ofs(s, a->rd + i), \
+ vreg_ofs(s, a->rs2 + i), \
+ s->vlen / 8, s->vlen / 8); \
+ } \
+ mark_vs_dirty(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
--
2.17.1
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, (continued)
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, frank . chang, 2020/07/22
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions,
frank . chang <=
- [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/22
- [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/22
- [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions, frank . chang, 2020/07/22
- [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/22