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[RFC PATCH 8/8] fpu/softfloat: define misc operation for bfloat16
From: |
LIU Zhiwei |
Subject: |
[RFC PATCH 8/8] fpu/softfloat: define misc operation for bfloat16 |
Date: |
Mon, 13 Jul 2020 07:45:21 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
fpu/softfloat-specialize.inc.c | 38 +++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 41 ++++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 6b778a7830..ff17f11f0c 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -259,6 +259,25 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
#endif
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the brain floating point value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+int bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return bfloat16_is_any_nan(a_);
+#else
+ uint16_t a = bfloat16_val(a_);
+ if (snan_bit_is_one(status)) {
+ return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
+ } else {
+ return ((a >> 6) & 0x1FF) == 0x1FF;
+ }
+#endif
+}
+
/*----------------------------------------------------------------------------
| Returns 1 if the half-precision floating-point value `a' is a signaling
| NaN; otherwise returns 0.
@@ -278,6 +297,25 @@ bool float16_is_signaling_nan(float16 a_, float_status
*status)
#endif
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the brain floating point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+int bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
+{
+#ifdef NO_SIGNALING_NANS
+ return 0;
+#else
+ uint16_t a = bfloat16_val(a_);
+ if (snan_bit_is_one(status)) {
+ return ((a >> 6) & 0x1FF) == 0x1FF;
+ } else {
+ return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
+ }
+#endif
+}
+
/*----------------------------------------------------------------------------
| Returns 1 if the single-precision floating-point value `a' is a quiet
| NaN; otherwise returns 0.
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 6590850253..d2c3f5fbe0 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -372,6 +372,47 @@ static inline float16 float16_set_sign(float16 a, int sign)
#define float16_three make_float16(0x4200)
#define float16_infinity make_float16(0x7c00)
+static inline int bfloat16_is_any_nan(bfloat16 a)
+{
+ return ((bfloat16_val(a) & ~0x8000) > 0x7F80);
+}
+
+static inline int bfloat16_is_neg(bfloat16 a)
+{
+ return bfloat16_val(a) >> 15;
+}
+
+static inline int bfloat16_is_infinity(bfloat16 a)
+{
+ return (bfloat16_val(a) & 0x7fff) == 0x7F80;
+}
+
+static inline int bfloat16_is_zero(bfloat16 a)
+{
+ return (bfloat16_val(a) & 0x7fff) == 0;
+}
+
+static inline int bfloat16_is_zero_or_denormal(bfloat16 a)
+{
+ return (bfloat16_val(a) & 0x7F80) == 0;
+}
+
+static inline bfloat16 bfloat16_abs(bfloat16 a)
+{
+ /* Note that abs does *not* handle NaN specially, nor does
+ * it flush denormal inputs to zero.
+ */
+ return make_bfloat16(bfloat16_val(a) & 0x7fff);
+}
+
+static inline bfloat16 bfloat16_chs(bfloat16 a)
+{
+ /* Note that chs does *not* handle NaN specially, nor does
+ * it flush denormal inputs to zero.
+ */
+ return make_bfloat16(bfloat16_val(a) ^ 0x8000);
+}
+
static inline bfloat16 bfloat16_set_sign(bfloat16 a, int sign)
{
return make_bfloat16((bfloat16_val(a) & 0x7fff) | (sign << 15));
--
2.23.0
- [RFC PATCH 0/8] Implement blfoat16 in softfloat, LIU Zhiwei, 2020/07/12
- [RFC PATCH 4/8] fpu/softfloat: add pack and unpack interfaces for bfloat16, LIU Zhiwei, 2020/07/12
- [RFC PATCH 7/8] fpu/softfloat: define covert operation for bfloat16, LIU Zhiwei, 2020/07/12
- [RFC PATCH 5/8] fpu/softfloat: define brain floating-point types, LIU Zhiwei, 2020/07/12
- [RFC PATCH 1/8] fpu/softfloat: fix up float16 nan recognition, LIU Zhiwei, 2020/07/12
- [RFC PATCH 8/8] fpu/softfloat: define misc operation for bfloat16,
LIU Zhiwei <=
- [RFC PATCH 2/8] fpu/softfloat: use the similiar logic to recognize sNaN and qNaN, LIU Zhiwei, 2020/07/12
- [RFC PATCH 6/8] fpu/softfloat: define operation for bfloat16, LIU Zhiwei, 2020/07/12
- [RFC PATCH 3/8] fpu/softfloat: add FloatFmt for bfloat16, LIU Zhiwei, 2020/07/12