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[RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions
From: |
frank . chang |
Subject: |
[RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions |
Date: |
Fri, 10 Jul 2020 18:48:58 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 7 ++++--
2 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index f441385f3a..59b25e17f8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2774,22 +2774,22 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
\
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_MM_TRANS(vmand_mm)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7a10b957df..6484c660c6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4731,6 +4731,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4740,8 +4741,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}
--
2.17.1
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, (continued)
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/10
- [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions, frank . chang, 2020/07/10
- [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction, frank . chang, 2020/07/10
- [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 61/65] fpu: fix float16 nan check, frank . chang, 2020/07/10
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/10
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/10
- [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions,
frank . chang <=
- [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/10
- [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add, frank . chang, 2020/07/10
- [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions, frank . chang, 2020/07/10