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[RFC 45/65] target/riscv: rvv-0.9: register gather instructions
From: |
frank . chang |
Subject: |
[RFC 45/65] target/riscv: rvv-0.9: register gather instructions |
Date: |
Fri, 10 Jul 2020 18:48:59 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 33 +++++++++++++++++--------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 59b25e17f8..50f9782a96 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2958,17 +2958,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
+ int ofs, int sew, bool sign)
{
switch (sew) {
case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld8s_i64(dest, base, ofs);
+ }
break;
case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld16s_i64(dest, base, ofs);
+ }
break;
case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld32s_i64(dest, base, ofs);
+ }
break;
case MO_64:
tcg_gen_ld_i64(dest, base, ofs);
@@ -3023,7 +3035,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64
dest,
/* Perform the load. */
load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
+ vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);
@@ -3041,9 +3053,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64
dest,
}
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
+ int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
@@ -3251,11 +3263,11 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
*a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen;
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
@@ -3282,7 +3294,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr
*a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen) {
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
+ if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
--
2.17.1
- [RFC 27/65] target/riscv: rvv-0.9: iota instruction, (continued)
- [RFC 27/65] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/10
- [RFC 28/65] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/10
- [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/10
- [RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions, frank . chang, 2020/07/10
- [RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions, frank . chang, 2020/07/10
- [RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions, frank . chang, 2020/07/10
- [RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions, frank . chang, 2020/07/10
- [RFC 45/65] target/riscv: rvv-0.9: register gather instructions,
frank . chang <=
- [RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions, frank . chang, 2020/07/10
- [RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions, frank . chang, 2020/07/10
- [RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions, frank . chang, 2020/07/10
- [RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf, frank . chang, 2020/07/10
- [RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10
- [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/10