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Re: [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes
From: |
Max Filippov |
Subject: |
Re: [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes |
Date: |
Wed, 8 Jul 2020 10:37:31 -0700 |
On Wed, Jul 8, 2020 at 9:25 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/6/20 4:47 PM, Max Filippov wrote:
> > +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
> > +{
> > + set_use_first_nan(true, &env->fp_status);
> > + return float64_add(a, b, &env->fp_status);
> > +}
> > +
> > float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
> > {
> > + set_use_first_nan(env->config->use_first_nan, &env->fp_status);
> > return float32_add(a, b, &env->fp_status);
> > }
>
> I think you can do better than to set the use_first_nan flag before every
> operation.
And it was better, until I found that the rules for float64 are a
bit... peculiar.
> E.g. the translator could remember the previous setting within the TB, only
> changing when necessary. E.g. if env->config->use_first_nan, then set it
> during reset and never change it again. Similarly if DFP is not enabled.
This thought crossed my mind too, but then set_use_first_nan only
sets one variable in the float_status and gets inlined.
Is it worth the trouble?
--
Thanks.
-- Max
- [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide, (continued)
- [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide, Max Filippov, 2020/07/06
- [PATCH 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/06
- [PATCH 10/21] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/06
- [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/06
- [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/06
- [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes, Max Filippov, 2020/07/06
[PATCH 15/21] tests/tcg/xtensa: update test_fp1 for DFPU, Max Filippov, 2020/07/06
[PATCH 13/21] tests/tcg/xtensa: expand madd tests, Max Filippov, 2020/07/06
[PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU, Max Filippov, 2020/07/06
[PATCH 16/21] tests/tcg/xtensa: update test_lsc for DFPU, Max Filippov, 2020/07/06
[PATCH 18/21] tests/tcg/xtensa: test double precision load/store, Max Filippov, 2020/07/06
[PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests, Max Filippov, 2020/07/06
[PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests, Max Filippov, 2020/07/06
[PATCH 20/21] target/xtensa: import DE_233L_FPU core, Max Filippov, 2020/07/06