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[PATCH rc6 17/30] target/avr: Initialize TCG register variables
From: |
Thomas Huth |
Subject: |
[PATCH rc6 17/30] target/avr: Initialize TCG register variables |
Date: |
Sun, 5 Jul 2020 16:03:02 +0200 |
From: Michael Rolnik <mrolnik@gmail.com>
Initialize TCG register variables.
Co-developed-by: Richard Henderson <richard.henderson@linaro.org>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
target/avr/translate.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index a6e67488df..becf096c12 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -129,6 +129,36 @@ struct DisasContext {
};
+void avr_cpu_tcg_init(void)
+{
+ int i;
+
+#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
+ cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
+ cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
+ cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
+ cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
+ cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
+ cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
+ cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
+ cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
+ cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
+ cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
+ cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
+ cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
+ cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
+ cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
+ cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
+ cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
+
+ for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
+ cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
+ reg_names[i]);
+ }
+#undef AVR_REG_OFFS
+}
+
+
static int to_regs_16_31_by_one(DisasContext *ctx, int indx)
{
return 16 + (indx % 16);
--
2.26.2
- [PATCH rc6 04/30] target/avr: CPU class: Add memory menagement support, (continued)
- [PATCH rc6 04/30] target/avr: CPU class: Add memory menagement support, Thomas Huth, 2020/07/05
- [PATCH rc6 03/30] target/avr: CPU class: Add interrupt handling support, Thomas Huth, 2020/07/05
- [PATCH rc6 02/30] target/avr: Introduce basic CPU class object, Thomas Huth, 2020/07/05
- [PATCH rc6 06/30] target/avr: CPU class: Add GDB support, Thomas Huth, 2020/07/05
- [PATCH rc6 08/30] target/avr: Add defintions of AVR core types, Thomas Huth, 2020/07/05
- [PATCH rc6 09/30] target/avr: Add instruction helpers, Thomas Huth, 2020/07/05
- [PATCH rc6 07/30] target/avr: Introduce enumeration AVRFeature, Thomas Huth, 2020/07/05
- [PATCH rc6 10/30] target/avr: Add instruction translation - Register definitions, Thomas Huth, 2020/07/05
- [PATCH rc6 11/30] target/avr: Add instruction translation - Arithmetic and Logic Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 14/30] target/avr: Add instruction translation - Bit and Bit-test Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 17/30] target/avr: Initialize TCG register variables,
Thomas Huth <=
- [PATCH rc6 13/30] target/avr: Add instruction translation - Data Transfer Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 12/30] target/avr: Add instruction translation - Branch Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 15/30] target/avr: Add instruction translation - MCU Control Instructions, Thomas Huth, 2020/07/05
- [PATCH rc6 16/30] target/avr: Add instruction translation - CPU main translation function, Thomas Huth, 2020/07/05
- [PATCH rc6 18/30] target/avr: Add support for disassembling via option '-d in_asm', Thomas Huth, 2020/07/05
- [PATCH rc6 19/30] hw/char: avr: Add limited support for USART peripheral, Thomas Huth, 2020/07/05
- [PATCH rc6 21/30] hw/misc: avr: Add limited support for power reduction device, Thomas Huth, 2020/07/05
- [PATCH rc6 20/30] hw/timer: avr: Add limited support for 16-bit timer peripheral, Thomas Huth, 2020/07/05
- [PATCH rc6 22/30] target/avr: Register AVR support with the rest of QEMU, Thomas Huth, 2020/07/05