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[PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update call
From: |
Alistair Francis |
Subject: |
[PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls |
Date: |
Fri, 26 Jun 2020 14:43:09 -0700 |
From: Jessica Clarke <jrtc27@jrtc27.com>
Claiming an interrupt and changing the source priority both potentially
affect whether an interrupt is pending, thus we must re-compute xEIP.
Note that we don't put the sifive_plic_update inside sifive_plic_claim
so that the logging of a claim (and the resulting IRQ) happens before
the state update, making the causal effect clear, and that we drop the
explicit call to sifive_plic_print_state when claiming since
sifive_plic_update already does that automatically at the end for us.
This can result in both spurious interrupt storms if you fail to
complete an IRQ before enabling interrupts (and no other actions occur
that result in a call to sifive_plic_update), but also more importantly
lost interrupts if a disabled interrupt is pending and then becomes
enabled.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200618210649.22451-1-jrtc27@jrtc27.com
Message-Id: <20200618210649.22451-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_plic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d91e82b8ab..c20c192034 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -255,8 +255,8 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr,
unsigned size)
plic->addr_config[addrid].hartid,
mode_to_char(plic->addr_config[addrid].mode),
value);
- sifive_plic_print_state(plic);
}
+ sifive_plic_update(plic);
return value;
}
}
@@ -287,6 +287,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr,
uint64_t value,
qemu_log("plic: write priority: irq=%d priority=%d\n",
irq, plic->source_priority[irq]);
}
+ sifive_plic_update(plic);
return;
} else if (addr >= plic->pending_base && /* 1 bit per source */
addr < plic->pending_base + (plic->num_sources >> 3))
--
2.27.0
- [PULL 00/63] riscv-to-apply queue, Alistair Francis, 2020/06/26
- [PULL 11/63] target/riscv: add vector amo operations, Alistair Francis, 2020/06/26
- [PULL 12/63] target/riscv: vector single-width integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 13/63] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 01/63] riscv: plic: Honour source priorities, Alistair Francis, 2020/06/26
- [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls,
Alistair Francis <=
- [PULL 04/63] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/06/26
- [PULL 15/63] target/riscv: vector bitwise logical instructions, Alistair Francis, 2020/06/26
- [PULL 05/63] target/riscv: support vector extension csr, Alistair Francis, 2020/06/26
- [PULL 16/63] target/riscv: vector single-width bit shift instructions, Alistair Francis, 2020/06/26
- [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, Alistair Francis, 2020/06/26
- [PULL 03/63] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/06/26
- [PULL 19/63] target/riscv: vector integer min/max instructions, Alistair Francis, 2020/06/26
- [PULL 35/63] target/riscv: vector widening floating-point multiply, Alistair Francis, 2020/06/26