Re: [Bug 1880355] [NEW] Length restrictions for fw_cfg_dma_transfer?

[Mark Cave-Ayland]

On 24/05/2020 14:40, Peter Maydell wrote:

> On Sun, 24 May 2020 at 11:30, Philippe Mathieu-Daudé <address@hidden> wrote:
>> It looks to me a normal behavior for a DMA device. DMA devices have a
>> different address space view than the CPUs.
>> Also note the fw_cfg is a generic device, not restricted to the x86 arch.
> 
> In an ideal world all our DMA devices would use some kind of common
> framework or design pattern so they didn't hog all the CPU
> and/or spend minutes with the BQL held if the guest requests
> an enormous-sized DMA. In practice many of them just have
> a simple "loop until the DMA transfer is complete" implementation...

One of the problems with the PPC Mac DBDMA emulation is that the controller is
effectively a mini-CPU that runs its own programs for transferring data to/from 
memory.

Currently this is done as a QEMU BH which means for larger transfers the 
emulated CPU
can be paused for a not insignificant amount of time until the program 
performing the
transfer finishes. I've always wondered if this should be running in a separate
thread to reduce its impact.


ATB,

Mark.