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[RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops
From: |
Stephen Long |
Subject: |
[RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops |
Date: |
Thu, 21 May 2020 12:24:54 -0700 |
Signed-off-by: Stephen Long <address@hidden>
---
sve2.risu | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 50ff756..ca14193 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -123,6 +123,31 @@ UMULLB A64_V 01000101 size:2 0 zm:5 011 110 zn:5
zd:5 \
UMULLT A64_V 01000101 size:2 0 zm:5 011 111 zn:5 zd:5 \
!constraints { $size != 0; }
+# Misc
+## bitwise shift left long
+SSHLLB A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 00 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SSHLLT A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 01 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+USHLLB A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 10 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+USHLLT A64_V 010001010 tszh:1 0 tszl:2 imm3:3 1010 11 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## integer add/subtract interleaved long
+SADDLBT A64_V 01000101 size:2 0 zm:5 1000 00 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBLBT A64_V 01000101 size:2 0 zm:5 1000 10 zn:5 zd:5 \
+!constraints { $size != 0; }
+SSUBLTB A64_V 01000101 size:2 0 zm:5 1000 11 zn:5 zd:5 \
+!constraints { $size != 0; }
+## bitwise exclusive-or interleaved
+EORBT A64_V 01000101 size:2 0 zm:5 10010 0 zn:5 zd:5
+EORTB A64_V 01000101 size:2 0 zm:5 10010 1 zn:5 zd:5
+## bitwise permute
+BEXT A64_V 01000101 size:2 0 zm:5 1011 00 zn:5 zd:5
+BDEP A64_V 01000101 size:2 0 zm:5 1011 01 zn:5 zd:5
+BGRP A64_V 01000101 size:2 0 zm:5 1011 10 zn:5 zd:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
- [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops, (continued)
- [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations, Stephen Long, 2020/05/21
- [RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops,
Stephen Long <=
- [RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated), Stephen Long, 2020/05/21
- [RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops, Stephen Long, 2020/05/21