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[RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops
From: |
Stephen Long |
Subject: |
[RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops |
Date: |
Thu, 21 May 2020 12:24:55 -0700 |
Signed-off-by: Stephen Long <address@hidden>
---
sve2.risu | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index ca14193..caca5c0 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -148,6 +148,42 @@ BEXT A64_V 01000101 size:2 0 zm:5 1011 00 zn:5
zd:5
BDEP A64_V 01000101 size:2 0 zm:5 1011 01 zn:5 zd:5
BGRP A64_V 01000101 size:2 0 zm:5 1011 10 zn:5 zd:5
+# Accumulate
+## complex integer add
+CADD A64_V 01000101 size:2 00000 0 11011 rot:1 zm:5 zdn:5
+SQCADD A64_V 01000101 size:2 00000 1 11011 rot:1 zm:5 zdn:5
+## integer absolute difference and accumulate long
+SABALB A64_V 01000101 size:2 0 zm:5 1100 00 zn:5 zda:5 \
+!constraints { $size != 0; }
+SABALT A64_V 01000101 size:2 0 zm:5 1100 01 zn:5 zda:5 \
+!constraints { $size != 0; }
+UABALB A64_V 01000101 size:2 0 zm:5 1100 10 zn:5 zda:5 \
+!constraints { $size != 0; }
+UABALT A64_V 01000101 size:2 0 zm:5 1100 11 zn:5 zda:5 \
+!constraints { $size != 0; }
+## integer add/subtract long with carry
+ADCLB A64_V 01000101 0 size:1 0 zm:5 11010 0 zn:5 zda:5
+ADCLT A64_V 01000101 0 size:1 0 zm:5 11010 1 zn:5 zda:5
+SBCLB A64_V 01000101 1 size:1 0 zm:5 11010 0 zn:5 zda:5
+SBCLT A64_V 01000101 1 size:1 0 zm:5 11010 1 zn:5 zda:5
+## bitwise shift right and accumulate
+SSRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 00 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+USRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 01 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SRSRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 10 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+URSRA A64_V 01000101 tszh:2 0 tszl:2 imm3:3 1110 11 zn:5 zda:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## bitwise shift and insert
+SRI A64_V 01000101 tszh:2 0 tszl:2 imm3:3 11110 0 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SLI A64_V 01000101 tszh:2 0 tszl:2 imm3:3 11110 1 zn:5 zd:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+## integer absolute difference and accumulate
+SABA A64_V 01000101 size:2 0 zm:5 11111 0 zn:5 zda:5
+UABA A64_V 01000101 size:2 0 zm:5 11111 1 zn:5 zda:5
+
# Floating Point Pairwise
FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
!constraints { $size != 0; }
--
2.25.1
- [RISU PATCH v2 00/22] Add risu patterns for SVE2 instructions, Stephen Long, 2020/05/21
- [RISU PATCH v2 04/22] sve2.risu: Add patterns for widening integer arithmetic ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 06/22] sve2.risu: Add patterns for accumulate ops,
Stephen Long <=
- [RISU PATCH v2 08/22] sve2.risu: Add patterns for character match insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 09/22] sve2.risu: Add patterns for histogram computation ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 07/22] sve2.risu: Add patterns for narrowing ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 11/22] sve2.risu: Add patterns for bitwise shift (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops, Stephen Long, 2020/05/21