Re: [PATCH] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature

[Paolo Bonzini]

On 13/04/20 08:52, Cathy Zhang wrote:
> AVX512_VP2INTERSECT compute vector pair intersection to a pair
> of mask registers, which is introduced with intel Tiger Lake,
> defining as CPUID.(EAX=7,ECX=0):EDX[bit 08].
> 
> Refer to the following release spec:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Cathy Zhang <address@hidden>
> ---
>  target/i386/cpu.c | 2 +-
>  target/i386/cpu.h | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 92fafa2..c8c95c3 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1078,7 +1078,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] 
> = {
>          .feat_names = {
>              NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
>              NULL, NULL, NULL, NULL,
> -            NULL, NULL, "md-clear", NULL,
> +            "avx512-vp2intersect", NULL, "md-clear", NULL,
>              NULL, NULL, NULL, NULL,
>              NULL, NULL, NULL /* pconfig */, NULL,
>              NULL, NULL, NULL, NULL,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 576f309..5c34795 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -770,6 +770,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_EDX_AVX512_4VNNIW     (1U << 2)
>  /* AVX512 Multiply Accumulation Single Precision */
>  #define CPUID_7_0_EDX_AVX512_4FMAPS     (1U << 3)
> +/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
> +#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
>  /* Speculation Control */
>  #define CPUID_7_0_EDX_SPEC_CTRL         (1U << 26)
>  /* Single Thread Indirect Branch Predictors */
> 

Queued, thanks.

Paolo