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Re: [PULL 17/45] target/arm: Vectorize SABA/UABA
From: |
Peter Maydell |
Subject: |
Re: [PULL 17/45] target/arm: Vectorize SABA/UABA |
Date: |
Thu, 21 May 2020 14:11:41 +0100 |
On Thu, 14 May 2020 at 15:22, Peter Maydell <address@hidden> wrote:
>
> From: Richard Henderson <address@hidden>
>
> Include 64-bit element size in preparation for SVE2.
Hi; Coverity points out that after this commit there is
dead code in disas_simd_3same_int():
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 54b06553a65..991e451644c 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -11197,6 +11197,13 @@ static void disas_simd_3same_int(DisasContext *s,
> uint32_t insn)
> gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size);
> }
> return;
> + case 0xf: /* SABA, UABA */
> + if (u) {
> + gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size);
> + } else {
> + gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size);
> + }
> + return;
Here case 0xf is handled entirely and we return early...
> case 0x10: /* ADD, SUB */
> if (u) {
> gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size);
> @@ -11329,16 +11336,6 @@ static void disas_simd_3same_int(DisasContext *s,
> uint32_t insn)
> genenvfn = fns[size][u];
> break;
> }
> - case 0xf: /* SABA, UABA */
> - {
> - static NeonGenTwoOpFn * const fns[3][2] = {
> - { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 },
> - { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 },
> - { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 },
> - };
> - genfn = fns[size][u];
> - break;
> - }
...and we did delete the "do the operation" code...
> case 0x16: /* SQDMULH, SQRDMULH */
> {
> static NeonGenTwoOpEnvFn * const fns[2][2] = {
...but we missed the handling of the accumulate part near the
bottom of the loop:
if (opcode == 0xf) {
/* SABA, UABA: accumulating ops */
static NeonGenTwoOpFn * const fns[3] = {
gen_helper_neon_add_u8,
gen_helper_neon_add_u16,
tcg_gen_add_i32,
};
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
fns[size](tcg_res, tcg_op1, tcg_res);
}
That whole if() is now dead and can be deleted. Richard, do
you want to send a patch?
thanks
-- PMM
- [PULL 12/45] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32, (continued)
- [PULL 12/45] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32, Peter Maydell, 2020/05/14
- [PULL 13/45] target/arm: Create gen_gvec_{qrdmla,qrdmls}, Peter Maydell, 2020/05/14
- [PULL 15/45] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*, Peter Maydell, 2020/05/14
- [PULL 14/45] target/arm: Pass pointer to qc to qrdmla/qrdmls, Peter Maydell, 2020/05/14
- [PULL 16/45] target/arm: Vectorize SABD/UABD, Peter Maydell, 2020/05/14
- [PULL 18/45] aspeed: Add support for the sonorapass-bmc board, Peter Maydell, 2020/05/14
- [PULL 20/45] hw/arm/virt: Introduce a RAS machine option, Peter Maydell, 2020/05/14
- [PULL 21/45] docs: APEI GHES generation and CPER record description, Peter Maydell, 2020/05/14
- [PULL 24/45] ACPI: Record the Generic Error Status Block address, Peter Maydell, 2020/05/14
- [PULL 17/45] target/arm: Vectorize SABA/UABA, Peter Maydell, 2020/05/14
- Re: [PULL 17/45] target/arm: Vectorize SABA/UABA,
Peter Maydell <=
- [PULL 25/45] KVM: Move hwpoison page related functions into kvm-all.c, Peter Maydell, 2020/05/14
- [PULL 30/45] target/arm: Convert Neon 3-reg-same SHA to decodetree, Peter Maydell, 2020/05/14
- [PULL 23/45] ACPI: Build Hardware Error Source Table, Peter Maydell, 2020/05/14
- [PULL 27/45] target-arm: kvm64: handle SIGBUS signal from kernel or KVM, Peter Maydell, 2020/05/14
- [PULL 19/45] acpi: nvdimm: change NVDIMM_UUID_LE to a common macro, Peter Maydell, 2020/05/14
- [PULL 22/45] ACPI: Build related register address fields via hardware error fw_cfg blob, Peter Maydell, 2020/05/14
- [PULL 28/45] MAINTAINERS: Add ACPI/HEST/GHES entries, Peter Maydell, 2020/05/14
- [PULL 26/45] ACPI: Record Generic Error Status Block(GESB) table, Peter Maydell, 2020/05/14