Hi folks:
i want to know about whether therr are limitations during qemu emulation systems, for exampe, did the regular bugs corener case cant be duplicated on qeme but exist on real boads?
why thing this is that , i have ever use hdl simulator (modsim and iverilog) and openrisc processor to emulate the linux and ucos running, and see the waveform of the simulateion process of the operations systems.
i found an interesting things, if i take just the tick interrupt as the only testbech event source,the kernel simulation waveform is identical duplicated again and again, which means i can predicate future behavior.
i think this something like qemu work principle and so want to know, whether the qemu has this limitation? is the simulation proces a "FSM" that with definition output if the input event are all regular and without random?
thank you