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[PULL 35/39] target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
From: |
Peter Maydell |
Subject: |
[PULL 35/39] target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree |
Date: |
Mon, 4 May 2020 13:33:05 +0100 |
Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/neon-dp.decode | 5 +++++
target/arm/translate-neon.inc.c | 14 ++++++++++++++
target/arm/translate.c | 21 ++-------------------
3 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index f62dbaa72d5..b721d39c7ba 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -54,5 +54,10 @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 ....
@3same_logic
VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
+VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
+VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
+VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
+VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
+
VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 507f0abe801..ab1740201c4 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -617,3 +617,17 @@ DO_3SAME(VEOR, tcg_gen_gvec_xor)
DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
+
+#define DO_3SAME_NO_SZ_3(INSN, FUNC) \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size == 3) { \
+ return false; \
+ } \
+ return do_3same(s, a, FUNC); \
+ }
+
+DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
+DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
+DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
+DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9affa92cbe7..2f054cfa783 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4899,25 +4899,6 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
return 0;
- case NEON_3R_VMAX:
- if (u) {
- tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- } else {
- tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- }
- return 0;
- case NEON_3R_VMIN:
- if (u) {
- tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- } else {
- tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- }
- return 0;
-
case NEON_3R_VSHL:
/* Note the operation is vshl vd,vm,vn */
tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
@@ -4926,6 +4907,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case NEON_3R_VADD_VSUB:
case NEON_3R_LOGIC:
+ case NEON_3R_VMAX:
+ case NEON_3R_VMIN:
/* Already handled by decodetree */
return 1;
}
--
2.20.1
- [PULL 23/39] target/arm: Convert VCMLA (vector) to decodetree, (continued)
- [PULL 23/39] target/arm: Convert VCMLA (vector) to decodetree, Peter Maydell, 2020/05/04
- [PULL 26/39] target/arm: Convert VFM[AS]L (vector) to decodetree, Peter Maydell, 2020/05/04
- [PULL 27/39] target/arm: Convert VCMLA (scalar) to decodetree, Peter Maydell, 2020/05/04
- [PULL 28/39] target/arm: Convert V[US]DOT (scalar) to decodetree, Peter Maydell, 2020/05/04
- [PULL 29/39] target/arm: Convert VFM[AS]L (scalar) to decodetree, Peter Maydell, 2020/05/04
- [PULL 30/39] target/arm: Convert Neon load/store multiple structures to decodetree, Peter Maydell, 2020/05/04
- [PULL 31/39] target/arm: Convert Neon 'load single structure to all lanes' to decodetree, Peter Maydell, 2020/05/04
- [PULL 34/39] target/arm: Convert Neon 3-reg-same logic ops to decodetree, Peter Maydell, 2020/05/04
- [PULL 32/39] target/arm: Convert Neon 'load/store single structure' to decodetree, Peter Maydell, 2020/05/04
- [PULL 33/39] target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree, Peter Maydell, 2020/05/04
- [PULL 35/39] target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree,
Peter Maydell <=
- [PULL 36/39] target/arm: Convert Neon 3-reg-same comparisons to decodetree, Peter Maydell, 2020/05/04
- [PULL 37/39] target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree, Peter Maydell, 2020/05/04
- [PULL 38/39] target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree, Peter Maydell, 2020/05/04
- [PULL 39/39] target/arm: Move gen_ function typedefs to translate.h, Peter Maydell, 2020/05/04
- Re: [PULL 00/39] target-arm queue, Peter Maydell, 2020/05/04
- Re: [PULL 00/39] target-arm queue, no-reply, 2020/05/05
- Re: [PULL 00/39] target-arm queue, no-reply, 2020/05/05