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[PATCH v2 07/15] target/arm: Wrap vector mla/mls GVecGen3 in GVecGen3Fn
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 07/15] target/arm: Wrap vector mla/mls GVecGen3 in GVecGen3Fn |
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Date: |
Sat, 2 May 2020 15:44:55 -0700 |
Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.h | 7 ++-
target/arm/translate-a64.c | 4 +-
target/arm/translate.c | 124 ++++++++++++++++++++-----------------
3 files changed, 74 insertions(+), 61 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 20ec9cedd7..4fbcdf1294 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -286,8 +286,11 @@ void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs,
uint32_t rm_ofs,
void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t opr_sz, uint32_t max_sz);
-extern const GVecGen3 mla_op[4];
-extern const GVecGen3 mls_op[4];
+void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
+
extern const GVecGen3 cmtst_op[4];
extern const GVecGen3 sshl_op[4];
extern const GVecGen3 ushl_op[4];
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8208651394..2b5ae4d43a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11243,9 +11243,9 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
return;
case 0x12: /* MLA, MLS */
if (u) {
- gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]);
+ gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mls, size);
} else {
- gen_gvec_op3(s, is_q, rd, rn, rm, &mla_op[size]);
+ gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
}
return;
case 0x11:
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b08c4a2527..da807242ff 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4792,62 +4792,69 @@ static void gen_mls_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
/* Note that while NEON does not support VMLA and VMLS as 64-bit ops,
* these tables are shared with AArch64 which does support them.
*/
+void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_mul_vec, INDEX_op_add_vec, 0
+ };
+ static const GVecGen3 ops[4] = {
+ { .fni4 = gen_mla8_i32,
+ .fniv = gen_mla_vec,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_8 },
+ { .fni4 = gen_mla16_i32,
+ .fniv = gen_mla_vec,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_16 },
+ { .fni4 = gen_mla32_i32,
+ .fniv = gen_mla_vec,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_32 },
+ { .fni8 = gen_mla64_i64,
+ .fniv = gen_mla_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
+}
-static const TCGOpcode vecop_list_mla[] = {
- INDEX_op_mul_vec, INDEX_op_add_vec, 0
-};
-
-static const TCGOpcode vecop_list_mls[] = {
- INDEX_op_mul_vec, INDEX_op_sub_vec, 0
-};
-
-const GVecGen3 mla_op[4] = {
- { .fni4 = gen_mla8_i32,
- .fniv = gen_mla_vec,
- .load_dest = true,
- .opt_opc = vecop_list_mla,
- .vece = MO_8 },
- { .fni4 = gen_mla16_i32,
- .fniv = gen_mla_vec,
- .load_dest = true,
- .opt_opc = vecop_list_mla,
- .vece = MO_16 },
- { .fni4 = gen_mla32_i32,
- .fniv = gen_mla_vec,
- .load_dest = true,
- .opt_opc = vecop_list_mla,
- .vece = MO_32 },
- { .fni8 = gen_mla64_i64,
- .fniv = gen_mla_vec,
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
- .load_dest = true,
- .opt_opc = vecop_list_mla,
- .vece = MO_64 },
-};
-
-const GVecGen3 mls_op[4] = {
- { .fni4 = gen_mls8_i32,
- .fniv = gen_mls_vec,
- .load_dest = true,
- .opt_opc = vecop_list_mls,
- .vece = MO_8 },
- { .fni4 = gen_mls16_i32,
- .fniv = gen_mls_vec,
- .load_dest = true,
- .opt_opc = vecop_list_mls,
- .vece = MO_16 },
- { .fni4 = gen_mls32_i32,
- .fniv = gen_mls_vec,
- .load_dest = true,
- .opt_opc = vecop_list_mls,
- .vece = MO_32 },
- { .fni8 = gen_mls64_i64,
- .fniv = gen_mls_vec,
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
- .load_dest = true,
- .opt_opc = vecop_list_mls,
- .vece = MO_64 },
-};
+void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_mul_vec, INDEX_op_sub_vec, 0
+ };
+ static const GVecGen3 ops[4] = {
+ { .fni4 = gen_mls8_i32,
+ .fniv = gen_mls_vec,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_8 },
+ { .fni4 = gen_mls16_i32,
+ .fniv = gen_mls_vec,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_16 },
+ { .fni4 = gen_mls32_i32,
+ .fniv = gen_mls_vec,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_32 },
+ { .fni8 = gen_mls64_i64,
+ .fniv = gen_mls_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
+}
/* CMTST : test is "if (X & Y != 0)". */
static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
@@ -5529,8 +5536,11 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
return 0;
case NEON_3R_VML: /* VMLA, VMLS */
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
- u ? &mls_op[size] : &mla_op[size]);
+ if (u) {
+ gen_gvec_mls(size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
+ } else {
+ gen_gvec_mla(size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
+ }
return 0;
case NEON_3R_VTST_VCEQ:
--
2.20.1
- [PATCH v2 03/15] target/arm: Create gen_gvec_{sri,sli}, (continued)
- [PATCH v2 03/15] target/arm: Create gen_gvec_{sri,sli}, Richard Henderson, 2020/05/02
- [PATCH v2 05/15] target/arm: Tidy handle_vec_simd_shri, Richard Henderson, 2020/05/02
- [PATCH v2 02/15] target/arm: Create gen_gvec_{u,s}{rshr,rsra}, Richard Henderson, 2020/05/02
- [PATCH v2 04/15] target/arm: Remove unnecessary range check for VSHL, Richard Henderson, 2020/05/02
- [PATCH v2 06/15] target/arm: Wrap vector compare zero GVecGen2 in GVecGen2Fn, Richard Henderson, 2020/05/02
- [PATCH v2 08/15] target/arm: Wrap vector cmtst/ushl/sshl GVecGen3 in GVecGen3Fn, Richard Henderson, 2020/05/02
- [PATCH v2 11/15] target/arm: Wrap vector qrdmla/qrdmls in GVecGen3Fn, Richard Henderson, 2020/05/02
- [PATCH v2 10/15] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32, Richard Henderson, 2020/05/02
- [PATCH v2 09/15] target/arm: Wrap vector uqadd/sqadd/uqsub/sqsub GVecGen4 in GVecGen3Fn, Richard Henderson, 2020/05/02
- [PATCH v2 12/15] target/arm: Pass pointer to qc to qrdmla/qrdmls, Richard Henderson, 2020/05/02
- [PATCH v2 07/15] target/arm: Wrap vector mla/mls GVecGen3 in GVecGen3Fn,
Richard Henderson <=
- [PATCH v2 13/15] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*, Richard Henderson, 2020/05/02
- [PATCH v2 14/15] target/arm: Vectorize SABD/UABD, Richard Henderson, 2020/05/02
- [PATCH v2 15/15] target/arm: Vectorize SABA/UABA, Richard Henderson, 2020/05/02
- Re: [PATCH v2 00/15] target/arm: partial vector cleanup, Peter Maydell, 2020/05/05