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[PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags
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From: |
Alistair Francis |
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Subject: |
[PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags |
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Date: |
Wed, 29 Apr 2020 11:28:46 -0700 |
When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Anup Patel <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
---
target/riscv/cpu_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d3ba9efb02..f36d184b7b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -452,10 +452,11 @@ restart:
hwaddr pte_addr;
if (two_stage && first_stage) {
+ int vbase_prot;
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, prot, base, access_type,
+ get_physical_address(env, &vbase, &vbase_prot, base, access_type,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;
--
2.26.2
- [PULL 00/14] RISC-V Patch Queue for 5.1, Alistair Francis, 2020/04/29
- [PULL 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/04/29
- [PULL 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL 05/14] riscv: AND stage-1 and stage-2 protection flags, Alistair Francis, 2020/04/29
- [PULL 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL 04/14] riscv: Don't use stage-2 PTE lookup protection flags,
Alistair Francis <=
- [PULL 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines, Alistair Francis, 2020/04/29
- [PULL 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option, Alistair Francis, 2020/04/29
- [PULL 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL 00/14] RISC-V Patch Queue for 5.1, Peter Maydell, 2020/04/29