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Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and s
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract |
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Date: |
Mon, 23 Mar 2020 10:46:53 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/23/20 1:10 AM, LIU Zhiwei wrote:
>> static void gen_gvec_rsubi(unsigned vece, uint32_t dofs,
>> uint32_t aofs, int64_t c,
>> uint32_t oprsz, uint32_t maxsz)
>> {
>> tcg_debug_assert(vece <= MO_64);
>> tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
>> }
> Hi Richard,
>
> When I try to add GVEC IR rsubs，I find it is some difficult to keep it
> separate from tcg-runtime-gvec.c.
>
> The .fno functions, e.g., gen_helper_gvec_rsubs8 need to be defined like
>
> void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
>
> {
>
> intptr_t oprsz = simd_oprsz(desc);
>
> vec8 vecb = (vec8)DUP16(b);
>
> intptr_t i;
>
> for (i = 0; i < oprsz; i += sizeof(vec8)) {
>
> *(vec8 *)(d + i) = vecb - *(vec8 *)(a + i);
>
> }
>
> clear_high(d, oprsz, desc);
>
> }
>
>
> The vec8 and DUP are defined in tcg-runtime-gvec.c.
Update your branch -- they're gone since commit 0a83e43a9ee6.
Just use normal integer types.
r~
- Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, (continued)
- [PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/12
- [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/12
- [PATCH v5 10/60] target/riscv: vector widening integer add and subtract, LIU Zhiwei, 2020/03/12
- [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 12/60] target/riscv: vector bitwise logical instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions, LIU Zhiwei, 2020/03/12