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[PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1 |
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Date: |
Fri, 31 Jan 2020 17:02:28 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e87c9115bc..455eb28907 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -130,9 +130,10 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
- if (env->priv == PRV_S &&
+ if ((env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TW)) {
+ get_field(env->mstatus, MSTATUS_TW)) ||
+ riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
--
2.25.0
- [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled, (continued)
- [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2020/01/31
- [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 14/35] target/riscv: Add virtual register swapping function, Alistair Francis, 2020/01/31
- [PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2020/01/31
- [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2020/01/31
- [PATCH v2 21/35] target/riscv: Add hypvervisor trap support, Alistair Francis, 2020/01/31
- [PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1,
Alistair Francis <=
- [PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2020/01/31
- [PATCH v2 22/35] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2020/01/31
- [PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 24/35] target/riscv: Remove the hret instruction, Alistair Francis, 2020/01/31
- [PATCH v2 23/35] target/riscv: Add hfence instructions, Alistair Francis, 2020/01/31
- [PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2020/01/31
- [PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2020/01/31
- [PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty, Alistair Francis, 2020/01/31
- [PATCH v2 29/35] target/riscv: Allow specifying MMU stage, Alistair Francis, 2020/01/31
- [PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2020/01/31