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[PATCH v2 09/35] target/riscv: Print priv and virt in disas log
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 09/35] target/riscv: Print priv and virt in disas log |
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Date: |
Fri, 31 Jan 2020 17:01:59 -0800 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 14dc71156b..afa2d6eea2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -808,7 +808,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
+ RISCVCPU *rvcpu = RISCV_CPU(cpu);
+ CPURISCVState *env = &rvcpu->env;
+#endif
+
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+#ifndef CONFIG_USER_ONLY
+ qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv,
env->virt);
+#endif
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
}
--
2.25.0
- [PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5, Alistair Francis, 2020/01/31
- [PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong, Alistair Francis, 2020/01/31
- [PATCH v2 02/35] target/riscv: Add the Hypervisor extension, Alistair Francis, 2020/01/31
- [PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2020/01/31
- [PATCH v2 04/35] target/riscv: Add support for the new execption numbers, Alistair Francis, 2020/01/31
- [PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs, Alistair Francis, 2020/01/31
- [PATCH v2 06/35] target/riscv: Add the virtulisation mode, Alistair Francis, 2020/01/31
- [PATCH v2 07/35] target/riscv: Add the force HS exception mode, Alistair Francis, 2020/01/31
- [PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2020/01/31
- [PATCH v2 09/35] target/riscv: Print priv and virt in disas log,
Alistair Francis <=
- [PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2020/01/31
- [PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2020/01/31
- [PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses, Alistair Francis, 2020/01/31
- [PATCH v2 14/35] target/riscv: Add virtual register swapping function, Alistair Francis, 2020/01/31
- [PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2020/01/31
- [PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2020/01/31
- [PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2020/01/31
- [PATCH v2 21/35] target/riscv: Add hypvervisor trap support, Alistair Francis, 2020/01/31