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[PULL 05/26] ftgmac100: check RX and TX buffer alignment
From: |
Peter Maydell |
Subject: |
[PULL 05/26] ftgmac100: check RX and TX buffer alignment |
Date: |
Thu, 30 Jan 2020 16:15:12 +0000 |
From: Cédric Le Goater <address@hidden>
These buffers should be aligned on 16 bytes.
Ignore invalid RX and TX buffer addresses and log an error. All
incoming and outgoing traffic will be dropped because no valid RX or
TX descriptors will be available.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/net/ftgmac100.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 4ad2594d3a6..2f92b65d4ef 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -198,6 +198,8 @@ typedef struct {
uint32_t des3;
} FTGMAC100Desc;
+#define FTGMAC100_DESC_ALIGNMENT 16
+
/*
* Specific RTL8211E MII Registers
*/
@@ -722,6 +724,12 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
s->itc = value;
break;
case FTGMAC100_RXR_BADR: /* Ring buffer address */
+ if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%"
+ HWADDR_PRIx "\n", __func__, value);
+ return;
+ }
+
s->rx_ring = value;
s->rx_descriptor = s->rx_ring;
break;
@@ -731,6 +739,11 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
break;
case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
+ if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%"
+ HWADDR_PRIx "\n", __func__, value);
+ return;
+ }
s->tx_ring = value;
s->tx_descriptor = s->tx_ring;
break;
--
2.20.1
- [PULL 00/26] target-arm queue, Peter Maydell, 2020/01/30
- [PULL 01/26] hw/core/or-irq: Fix incorrect assert forbidding num-lines == MAX_OR_LINES, Peter Maydell, 2020/01/30
- [PULL 02/26] target/arm/arm-semi: Don't let the guest close stdin/stdout/stderr, Peter Maydell, 2020/01/30
- [PULL 04/26] hw/arm: ast2600: Wire up the eMMC controller, Peter Maydell, 2020/01/30
- [PULL 03/26] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model, Peter Maydell, 2020/01/30
- [PULL 05/26] ftgmac100: check RX and TX buffer alignment,
Peter Maydell <=
- [PULL 06/26] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0, Peter Maydell, 2020/01/30
- [PULL 07/26] misc/pca9552: Add qom set and get, Peter Maydell, 2020/01/30
- [PULL 09/26] add device_legacy_reset function to prepare for reset api change, Peter Maydell, 2020/01/30
- [PULL 08/26] hw/arm/raspi: Remove obsolete use of -smp to set the soc 'enabled-cpus', Peter Maydell, 2020/01/30
- [PULL 10/26] hw/core/qdev: add trace events to help with resettable transition, Peter Maydell, 2020/01/30
- [PULL 12/26] hw/core: add Resettable support to BusClass and DeviceClass, Peter Maydell, 2020/01/30
- [PULL 14/26] hw/core/qdev: handle parent bus change regarding resettable, Peter Maydell, 2020/01/30
- [PULL 13/26] hw/core/resettable: add support for changing parent, Peter Maydell, 2020/01/30
- [PULL 16/26] hw/core: deprecate old reset functions and introduce new ones, Peter Maydell, 2020/01/30
- [PULL 19/26] hw/s390x/ipl: replace deprecated qdev_reset_all registration, Peter Maydell, 2020/01/30