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[RFC v3 15/25] intel_iommu: process pasid cache invalidation
From: |
Liu, Yi L |
Subject: |
[RFC v3 15/25] intel_iommu: process pasid cache invalidation |
Date: |
Wed, 29 Jan 2020 04:16:46 -0800 |
From: Liu Yi L <address@hidden>
This patch adds PASID cache invalidation handling. When guest enabled
PASID usages (e.g. SVA), guest software should issue a proper PASID
cache invalidation when caching-mode is exposed. This patch only adds
the draft handling of pasid cache invalidation. Detailed handling will
be added in subsequent patches.
Cc: Kevin Tian <address@hidden>
Cc: Jacob Pan <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: Yi Sun <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Signed-off-by: Liu Yi L <address@hidden>
---
hw/i386/intel_iommu.c | 66 ++++++++++++++++++++++++++++++++++++++----
hw/i386/intel_iommu_internal.h | 12 ++++++++
hw/i386/trace-events | 3 ++
3 files changed, 76 insertions(+), 5 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 43a728f..58e7213 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2393,6 +2393,63 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
return true;
}
+static int vtd_pasid_cache_dsi(IntelIOMMUState *s, uint16_t domain_id)
+{
+ return 0;
+}
+
+static int vtd_pasid_cache_psi(IntelIOMMUState *s,
+ uint16_t domain_id, uint32_t pasid)
+{
+ return 0;
+}
+
+static int vtd_pasid_cache_gsi(IntelIOMMUState *s)
+{
+ return 0;
+}
+
+static bool vtd_process_pasid_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ uint16_t domain_id;
+ uint32_t pasid;
+ int ret = 0;
+
+ if ((inv_desc->val[0] & VTD_INV_DESC_PASIDC_RSVD_VAL0) ||
+ (inv_desc->val[1] & VTD_INV_DESC_PASIDC_RSVD_VAL1) ||
+ (inv_desc->val[2] & VTD_INV_DESC_PASIDC_RSVD_VAL2) ||
+ (inv_desc->val[3] & VTD_INV_DESC_PASIDC_RSVD_VAL3)) {
+ error_report_once("non-zero-field-in-pc_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ domain_id = VTD_INV_DESC_PASIDC_DID(inv_desc->val[0]);
+ pasid = VTD_INV_DESC_PASIDC_PASID(inv_desc->val[0]);
+
+ switch (inv_desc->val[0] & VTD_INV_DESC_PASIDC_G) {
+ case VTD_INV_DESC_PASIDC_DSI:
+ ret = vtd_pasid_cache_dsi(s, domain_id);
+ break;
+
+ case VTD_INV_DESC_PASIDC_PASID_SI:
+ ret = vtd_pasid_cache_psi(s, domain_id, pasid);
+ break;
+
+ case VTD_INV_DESC_PASIDC_GLOBAL:
+ ret = vtd_pasid_cache_gsi(s);
+ break;
+
+ default:
+ error_report_once("invalid-inv-granu-in-pc_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ return (ret == 0) ? true : false;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -2499,12 +2556,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
- /*
- * TODO: the entity of below two cases will be implemented in future
series.
- * To make guest (which integrates scalable mode support patch set in
- * iommu driver) work, just return true is enough so far.
- */
case VTD_INV_DESC_PC:
+ trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]);
+ if (!vtd_process_pasid_desc(s, &inv_desc)) {
+ return false;
+ }
break;
case VTD_INV_DESC_PIOTLB:
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index fb5fdc2..6c03560 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -448,6 +448,18 @@ typedef union VTDInvDesc VTDInvDesc;
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
+#define VTD_INV_DESC_PASIDC_G (3ULL << 4)
+#define VTD_INV_DESC_PASIDC_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PASIDC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000ffc0ULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL1 0xffffffffffffffffULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL2 0xffffffffffffffffULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL3 0xffffffffffffffffULL
+
+#define VTD_INV_DESC_PASIDC_DSI (0ULL << 4)
+#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4)
+#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4)
+
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
uint16_t domain_id;
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index 71536a7..f7cd4e5 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -22,6 +22,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d"
vtd_inv_qi_tail(uint16_t head) "write tail %d"
vtd_inv_qi_fetch(void) ""
vtd_context_cache_reset(void) ""
+vtd_pasid_cache_gsi(void) ""
+vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation domain
0x%"PRIx16
+vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC
invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32
vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present"
vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"
devfn %"PRIu8" not present"
vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t
domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64"
domain 0x%"PRIx16
--
2.7.4
- [RFC v3 08/25] vfio: pass IOMMUContext into vfio_get_group(), (continued)
- [RFC v3 08/25] vfio: pass IOMMUContext into vfio_get_group(), Liu, Yi L, 2020/01/29
- [RFC v3 02/25] hw/iommu: introduce DualStageIOMMUObject, Liu, Yi L, 2020/01/29
- [RFC v3 07/25] header file update VFIO/IOMMU vSVA APIs, Liu, Yi L, 2020/01/29
- [RFC v3 05/25] intel_iommu: provide get_iommu_context() callback, Liu, Yi L, 2020/01/29
- [RFC v3 03/25] hw/iommu: introduce IOMMUContext, Liu, Yi L, 2020/01/29
- [RFC v3 10/25] vfio: register DualStageIOMMUObject to vIOMMU, Liu, Yi L, 2020/01/29
- [RFC v3 01/25] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps, Liu, Yi L, 2020/01/29
- [RFC v3 12/25] vfio/common: add pasid_alloc/free support, Liu, Yi L, 2020/01/29
- [RFC v3 13/25] intel_iommu: modify x-scalable-mode to be string option, Liu, Yi L, 2020/01/29
- [RFC v3 11/25] vfio: get stage-1 pasid formats from Kernel, Liu, Yi L, 2020/01/29
- [RFC v3 15/25] intel_iommu: process pasid cache invalidation,
Liu, Yi L <=
- [RFC v3 14/25] intel_iommu: add virtual command capability support, Liu, Yi L, 2020/01/29
- [RFC v3 16/25] intel_iommu: add PASID cache management infrastructure, Liu, Yi L, 2020/01/29
- [RFC v3 17/25] vfio: add bind stage-1 page table support, Liu, Yi L, 2020/01/29
- [RFC v3 18/25] intel_iommu: bind/unbind guest page table to host, Liu, Yi L, 2020/01/29
- [RFC v3 19/25] intel_iommu: replay guest pasid bindings to host, Liu, Yi L, 2020/01/29
- [RFC v3 20/25] intel_iommu: replay pasid binds after context cache invalidation, Liu, Yi L, 2020/01/29
- [RFC v3 22/25] vfio: add support for flush iommu stage-1 cache, Liu, Yi L, 2020/01/29
- [RFC v3 21/25] intel_iommu: do not pass down pasid bind for PASID #0, Liu, Yi L, 2020/01/29
- [RFC v3 23/25] intel_iommu: process PASID-based iotlb invalidation, Liu, Yi L, 2020/01/29
- [RFC v3 24/25] intel_iommu: propagate PASID-based iotlb invalidation to host, Liu, Yi L, 2020/01/29