[PATCH v4 0/7] target/mips: Misc MIPS fixes and improvements for 5.0

[Aleksandar Markovic]

From: Aleksandar Markovic <address@hidden>

This series contains a variety of fixes and improvements for
target MIPS.

v3->v4:

  - split micromips R6 disassembler patch to more manageable parts
  - added new field to disassemble_info structure
  - CRC32 refactoring is as is in this version, but refactoring is
    planned for near future

v2->v3:

  - added micromips R6 disassembler

Aleksandar Markovic (5):
  target/mips: Rectify documentation on deprecating r4k machine
  target/mips: Add support for MIPS<32|64>R6 CRC32 ISA
  disas: Add a field for target-dependant data
  disas: mips: Add micromips R6 disassembler - infrastructure and 16-bit
    instructions
  disas: mips: Add micromips R6 disassembler - 32-bit instructions

Yongbok Kim (2):
  target/mips: Amend CP0 WatchHi register implementation
  target/mips: Add implementation of GINVT instruction

 disas/Makefile.objs     |    1 +
 disas/micromips_r6.c    | 5670 +++++++++++++++++++++++++++++++++++++++++++++++
 disas/mips.c            |   10 +
 include/disas/dis-asm.h |    4 +
 qemu-deprecated.texi    |    2 +-
 target/mips/cpu.c       |    4 +
 target/mips/cpu.h       |    4 +-
 target/mips/helper.c    |   20 +-
 target/mips/helper.h    |    7 +
 target/mips/internal.h  |    1 +
 target/mips/machine.c   |    6 +-
 target/mips/op_helper.c |  171 +-
 target/mips/translate.c |  215 +-
 13 files changed, 6081 insertions(+), 34 deletions(-)
 create mode 100644 disas/micromips_r6.c

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2.7.4