[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize()
From: |
Palmer Dabbelt |
Subject: |
[PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize() |
Date: |
Tue, 21 Jan 2020 14:56:58 -0800 |
From: Pan Nengyuan <address@hidden>
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95732..0e12b3ccef 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_U_PLIC].size);
+ g_free(plic_hart_config);
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
--
2.25.0.341.g760bfbb309-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Palmer Dabbelt, 2020/01/21
- [PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize(),
Palmer Dabbelt <=
- [PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state, Palmer Dabbelt, 2020/01/21
- [PULL 3/5] target/riscv: Fix tb->flags FS status, Palmer Dabbelt, 2020/01/21
- [PULL 2/5] riscv: Set xPIE to 1 after xRET, Palmer Dabbelt, 2020/01/21
- [PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty, Palmer Dabbelt, 2020/01/21
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Peter Maydell, 2020/01/23
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Palmer Dabbelt, 2020/01/23
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1, Peter Maydell, 2020/01/24