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[PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instruct
From: |
Ian Jiang |
Subject: |
[PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions |
Date: |
Tue, 21 Jan 2020 18:07:32 +0800 |
According to the RISC-V specification, when executing an MRET or SRET
instruction, xPIE in mstatus or sstatus should be set to 1. The orginal
QEMU does not give the right operations.
This patch fix the problem.
Signed-off-by: Ian Jiang <address@hidden>
---
target/riscv/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36232..e87c9115bc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_SIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_SPIE));
- mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
@@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_MPIE));
- mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
--
2.17.1
- [PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions,
Ian Jiang <=