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Re: [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF |
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Date: |
Thu, 16 Jan 2020 14:51:02 -1000 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 |
On 1/10/20 11:28 AM, Stafford Horne wrote:
> The mask used when setting FPCSR allows setting bits 10 to 1. However,
> OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
> Flag (DZF). This seems like an off-by-one bug.
>
> This was found when testing the GLIBC test suite which has test cases to
> set and clear all bits.
>
> Signed-off-by: Stafford Horne <address@hidden>
> ---
> target/openrisc/fpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks, queued.
r~