Re: [PATCH v5 12/22] target/arm: generate xml description of our SVE registers

[Richard Henderson]

On 1/14/20 5:09 AM, Alex Bennée wrote:
> We also expose a the helpers to read/write the the registers.
> 
> Signed-off-by: Alex Bennée <address@hidden>
> 
> ---
> v2
>   - instead of zNpM expose zN at sve_max_vq width
>   - wrap union in union q(us), d(usf), s(usf), h(usf), b(us)
> v3
>   - add a vg pseudo register for current width
>   - spacing fixes
>   - use switch/case for whole group
>   - drop fpsr_pos marker
>   - remove unused variables
> v4
>   - const-ify vec_lanes
>   - drop vg

Sigh.  This still feels like we're coding to a gdb bug.

I assert that vg (or equivalent information) is required for the job to be done
correctly.  It's a per-core and therefore, for user-space, per-thread quantity.
 We cannot possibly be "changing targets" for the "thread N" command.

I'll give you an
Acked-by: Richard Henderson <address@hidden>

because I recognize that this is how gdb works today, but I don't like it.


r~