Re: [PATCH 4/7] target/ppc: Add SPR TBU40

[Philippe Mathieu-Daudé]

On 11/28/19 2:46 PM, Cédric Le Goater wrote:
> From: Suraj Jitindar Singh <address@hidden>
>
> The spr TBU40 is used to set the upper 40 bits of the timebase
> register, present on POWER5+ and later processors.
>
> This register can only be written by the hypervisor, and cannot be read.
>
> Signed-off-by: Suraj Jitindar Singh <address@hidden>
> Reviewed-by: David Gibson <address@hidden>
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
>   target/ppc/cpu.h                |  1 +
>   target/ppc/helper.h             |  1 +
>   hw/ppc/ppc.c                    | 13 +++++++++++++
>   target/ppc/timebase_helper.c    |  5 +++++
>   target/ppc/translate_init.inc.c | 19 +++++++++++++++++++
>   5 files changed, 39 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 646a94370dba..8ffcfa0ea162 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1312,6 +1312,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env);
>   void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
>   target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
>   void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
> +void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
>   uint64_t cpu_ppc_load_purr(CPUPPCState *env);
>   void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
>   uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 356a14d8a639..cd0dfe383a2a 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -672,6 +672,7 @@ DEF_HELPER_FLAGS_2(store_decr, TCG_CALL_NO_RWG, void, env, 
> tl)
>   DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env)
>   DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
>   DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
> +DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl)
>   DEF_HELPER_2(store_hid0_601, void, env, tl)
>   DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
>   DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index 353f11b91d40..3666e58865b3 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -710,6 +710,19 @@ void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
>                        &tb_env->vtb_offset, value);
>   }
>   
> +void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
> +{
> +    ppc_tb_t *tb_env = env->tb_env;
> +    uint64_t tb;
> +
> +    tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
> +                        tb_env->tb_offset);
> +    tb &= 0xFFFFFFUL;
> +    tb |= (value & ~0xFFFFFFUL);

IMHO easier to review as:

       tb = deposit64(value, 0, 40, tb);

> +    cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
> +                     &tb_env->tb_offset, tb);
> +}
> +
>   static void cpu_ppc_tb_stop (CPUPPCState *env)
>   {
>       ppc_tb_t *tb_env = env->tb_env;
> diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
> index 2395295b778c..703bd9ed18b9 100644
> --- a/target/ppc/timebase_helper.c
> +++ b/target/ppc/timebase_helper.c
> @@ -128,6 +128,11 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val)
>       cpu_ppc_store_vtb(env, val);
>   }
>   
> +void helper_store_tbu40(CPUPPCState *env, target_ulong val)
> +{
> +    cpu_ppc_store_tbu40(env, val);
> +}
> +
>   target_ulong helper_load_40x_pit(CPUPPCState *env)
>   {
>       return load_40x_pit(env);
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index a3cf1d8a450c..9815df6f77c8 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -327,6 +327,11 @@ static void spr_write_vtb(DisasContext *ctx, int sprn, int 
> gprn)
>       gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
>   }
>   
> +static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> +{
> +    gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> +}
> +
>   #endif
>   #endif
>   
> @@ -7848,6 +7853,16 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
>                    0x00000000);
>   }
>   
> +static void gen_spr_power5p_tb(CPUPPCState *env)
> +{
> +    /* TBU40 (High 40 bits of the Timebase register */
> +    spr_register_hv(env, SPR_TBU40, "TBU40",
> +                    SPR_NOACCESS, SPR_NOACCESS,
> +                    SPR_NOACCESS, SPR_NOACCESS,
> +                    SPR_NOACCESS, &spr_write_tbu40,
> +                    0x00000000);
> +}
> +
>   #if !defined(CONFIG_USER_ONLY)
>   static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
>   {
> @@ -8399,6 +8414,7 @@ static void init_proc_power5plus(CPUPPCState *env)
>       gen_spr_power5p_common(env);
>       gen_spr_power5p_lpar(env);
>       gen_spr_power5p_ear(env);
> +    gen_spr_power5p_tb(env);
>   
>       /* env variables */
>       env->dcache_line_size = 128;
> @@ -8511,6 +8527,7 @@ static void init_proc_POWER7(CPUPPCState *env)
>       gen_spr_power5p_common(env);
>       gen_spr_power5p_lpar(env);
>       gen_spr_power5p_ear(env);
> +    gen_spr_power5p_tb(env);
>       gen_spr_power6_common(env);
>       gen_spr_power6_dbg(env);
>       gen_spr_power7_book4(env);
> @@ -8652,6 +8669,7 @@ static void init_proc_POWER8(CPUPPCState *env)
>       gen_spr_power5p_common(env);
>       gen_spr_power5p_lpar(env);
>       gen_spr_power5p_ear(env);
> +    gen_spr_power5p_tb(env);
>       gen_spr_power6_common(env);
>       gen_spr_power6_dbg(env);
>       gen_spr_power8_tce_address_control(env);
> @@ -8842,6 +8860,7 @@ static void init_proc_POWER9(CPUPPCState *env)
>       gen_spr_power5p_common(env);
>       gen_spr_power5p_lpar(env);
>       gen_spr_power5p_ear(env);
> +    gen_spr_power5p_tb(env);
>       gen_spr_power6_common(env);
>       gen_spr_power6_dbg(env);
>       gen_spr_power8_tce_address_control(env);