Re: riscv: How to debug a wrong pc after executing ret instruction?

[Bin Meng]

On Wed, Jan 8, 2020 at 5:23 PM Ian Jiang <address@hidden> wrote:
>
> Problem
> ======
> The next instruction after executing "ret" (i.e. jalr x0, 0(x1)) is not at 
> 0x000000008000056c (x1/ra) as expected,  but at  0x000000008000056c.

I don't get this. is not at address A but at address B, but you wrote
A and B exactly the same?

> How to debug this issue? Any suggestion is appreciated.
>
> QEMU command
> =============
> qemu-system-riscv64 -nographic -machine virt -kernel my-test.elf -smp 1 -d 
> in_asm,cpu
>
> Trace (piece)
> ===========
> IN:
> 0x0000000081150000:  00259eb7  lui t4,2461696
> 0x0000000081150004:  00099b37  lui s6,626688
> 0x0000000081150008:  01db3023  sd t4,0(s6)
> 0x000000008115000c:  00008067  ret
>
> pc        0000000081150000
> x1/ra    000000008000056c
>
> IN:
> 0x0000000080003da0: 10503023  sd t0,256(zero)
> ...
>
>
> QEMU version
> ===========
> upstream tag v4.2.0
>

Regards,
Bin