If user provided non-sense RAM size, board will complain and
continue running with max RAM size supported.
Also RAM is going to be allocated by generic code, so it won't be
possible for board to fix things up for user.
Make it error message and exit to force user fix CLI,
instead of accepting non-sense CLI values.
Signed-off-by: Igor Mammedov <address@hidden>
---
include/hw/ppc/ppc4xx.h | 9 ++++-----
hw/ppc/ppc440_bamboo.c | 11 ++++-------
hw/ppc/ppc4xx_devs.c | 26 ++++++++++++++++----------
hw/ppc/sam460ex.c | 5 ++---
4 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 7d82259..1a28127 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -42,11 +42,10 @@ enum {
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
-ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[],
- hwaddr ram_sizes[],
- const ram_addr_t sdram_bank_sizes[]);
+void ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
+ hwaddr ram_bases[], hwaddr ram_sizes[],
+ const ram_addr_t sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 4d95c0f..66dee89 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -162,7 +162,6 @@ static void main_cpu_reset(void *opaque)
static void bamboo_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -207,10 +206,8 @@ static void bamboo_init(MachineState *machine)
/* SDRAM controller */
memset(ram_bases, 0, sizeof(ram_bases));
memset(ram_sizes, 0, sizeof(ram_sizes));
- ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS,
- ram_memories,
- ram_bases, ram_sizes,
- ppc440ep_sdram_bank_sizes);
+ ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS, ram_memories,
+ ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, 1);
@@ -272,7 +269,7 @@ static void bamboo_init(MachineState *machine)
/* Load initrd. */
if (initrd_filename) {
initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
- ram_size - RAMDISK_ADDR);
+ machine->ram_size - RAMDISK_ADDR);
if (initrd_size < 0) {
error_report("could not load ram disk '%s' at %x",
@@ -283,7 +280,7 @@ static void bamboo_init(MachineState *machine)
/* If we're loading a kernel directly, we must load the device tree too. */
if (kernel_filename) {
- if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR,
+ if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
initrd_size, kernel_cmdline) < 0) {
error_report("couldn't load device tree");
exit(1);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index c2e5013..54af296 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -673,11 +673,10 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq,
int nbanks,
* The 4xx SDRAM controller supports a small number of banks, and each bank
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
-ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[],
- hwaddr ram_sizes[],
- const ram_addr_t sdram_bank_sizes[])
+void ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
+ hwaddr ram_bases[], hwaddr ram_sizes[],
+ const ram_addr_t sdram_bank_sizes[])
{
MemoryRegion *ram = g_malloc0(sizeof(*ram));
ram_addr_t size_left = ram_size;
@@ -699,10 +698,19 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int
nr_banks,
}
}
- ram_size -= size_left;
if (size_left) {
- error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM"
- " controller limits", ram_size / MiB);
+ char *s = g_strdup("");
+ for (i = 0; sdram_bank_sizes[i]; i++) {
+ char *t = g_strdup_printf("%s%" PRIi64 "%s", s,
sdram_bank_sizes[i],
+ sdram_bank_sizes[i + 1] ? " ," : "");
+ g_free(s);
+ s = t;
+ }
+ error_report("Invalid RAM size, unable to fit all RAM into RAM banks"
+ " (unassigned RAM: %" PRIi64 ")", size_left);
+ error_report("Supported: %d banks and sizes/bank: %s", nr_banks, s);
+ g_free(s);
+ exit(EXIT_FAILURE);
}
memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);
@@ -725,8 +733,6 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int
nr_banks,
}
}
}
-
- return ram_size;
}
/*****************************************************************************/
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 437e214..f592816 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -324,9 +324,8 @@ static void sam460ex_init(MachineState *machine)
/* SDRAM controller */
/* put all RAM on first bank because board has one slot
* and firmware only checks that */
- machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
- ram_memories, ram_bases, ram_sizes,
- ppc460ex_sdram_bank_sizes);
+ ppc4xx_sdram_adjust(machine->ram_size, 1, ram_memories, ram_bases,
+ ram_sizes, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,